The goal is to define a common pad frame for at least the large chips of the machine, (e.g. cache, memory controller, IOB, display controller and map cache), so that we can share a common probe card, bonding map, and hopefully tester configuration. For that reason, pads should not be edited, and it should be clear that standardization is a plus and unnecessary customization is a nuisance.

To get the pads, bringover /Indigo/Dragon7.0/Top/DynaBusInterface.df and DynabusPads.dale contains the pads.

A standard probe card will be designed that will probe the 268 possible pad positions, (with the exception of the 64 dynabus data output pads). For that reason, all the pad locations must contain a pad, even if unused in that particular chip.

The PGA has an inside ring of signal tabs and an outside ring of large power tabs. There are 67 signal tabs on a 250m pitch per side (total 268). Each side has 8 power tabs, alternating between power and ground. The corners power tabs are truncated. The cavity is 17.75mm, or large enough to accomodate any circuit we can currently dream of. For too small a chip, long bonding wires might actually be a problem.

The pad pitch is 180m (7 mils) per pad. On the full pad frame this creates a cavity of 12.060mm for the inner. Adding twice the pad height (700m per pad) leads to a square chip of 13.46mm on a side.

The pad opening is 100m (4 mils), which Pentronix and most bonding houses in the Valley (but not VTI) can accomodate.

Power pads are located on the periphery of the die, and match the power fingers on the package. The pattern for the top row is:

Then you need to rotate it to get the other sides. I insist on rotation, no symetry!

These pads contain a chunk of the double decker bus that carries power to the circuit. The width of 200m is chosen. This ensures a maximum current density of 100mA for metal1 and 200mA for metal2. Output pad produce a spike of 50mA and an average current of 5mA. Since at most 5 pads rely on a given section of the bus for their power, the average current density should not exceed 25mA. This leaves a comfortable margin for the rest of the circuit. The resistance of a section of the bus 1mm long is 30mW*1000/200=0.15W; with a 5*50mA=250mA spike when all pads fire simultaneously, the voltage drop is less than 40mV.

Pins:

The last stage of drivers can deliver about 50mA under 5V. It drives a 40pF load in a couple of ns. The drains of the n transistor (w=500m) and of the p transistor (w=1100m) are protected by guard rings and act as clamping diode. Spikes of up to 1000V (from a 100pF capacitor through 2kW) did not hurt the circuit. Each pad receives power from the outside power bus (the double decker) and passes some of it to the inside of the circuit.

The pad can be used as

This pad should be used instead of a blank space on the pad frame. There is a bonding site which is unconnected. The only function of the pad is to pass Vdd and Gnd to the inside of the chip. Could be replaced by a power pad if I decide to provide them.

One Vdd and one Gnd. Is it necessary with the outside row of power pads ?

The clock is input through a regular input pad, and amplified through two buffers distributed throughout the standard cell blocks. This ensures that the clock is generated where it is needed, and the size of the buffers is tailored for each chip.

The amplified clock is then output through a simple metal pad to be sampled inside the BIC. Actual zapping tests showed that ESD-induced latchup was not an issue.

Grant is input through a regular input pad and latched. The nQ output of the flop goes through 3 buffers (drive=2, 8, 32) and is distributed to the pads. The delay from rising edge of clock to data valid on bus was found to be about 8ns. The schematics is provided for your simulating and nit-picking pleasure.

In order to save probes, one can use the output side of an input-only pad (say X) for testing an output only signal (say Y). Y is connected to the dataIn pin of X and a global "test" signal to the enable, so the X pad is used as a bidirectional pad, and the Y pad is not probed. This saves probes, but not tester resources, at least on the present tester.

Let's picture a worst case chip by making the following hypothesis:

Justifications: (1) the IOBridge is the largest SC block we have placed, and combinatorial logic produces switches in successive waves, producing smaller spikes; (2) and (3) result from elementary remarks about cell sizes and die size.

So, we reduce the problem to half a row, holding 15 flops, powered through a 5mm long by 10m wide metal1 line. Since metal has a resistivity of 30mW/¡, the resistance is 15W.

Now we know that a switching flop produces a spike of 2.2mA (SPICE simulation) and we can suppose that at worst, all flops switch simultaneously. The resulting spike of 33mA will produce a voltage drop of 495mV. (what about capa and inductance?)

Assuming a 40MHz clock rate, the average current through one flop is about 0.176mA; the half-row will thus need 2.64mA of current. (see CLC for a better figure)

Measuring of total capacitance of all nodes in a circuit (IOB) leads to a value of 5.5nF; assuming a 20MHz clock and an equal distribution between up and down-going nodes, the average intensity comes up to 1/2 * 5.5nF * 5V / 50ns = 275mA and the power dissipation to 1.4W.

This figures lead to 275mA average current for the inner of the chip: it takes 100m of metal2 or 200m of metal1 to provide this power.

A typical load on the wire wrapped machine was build and measured. In the region we plan to use the circuits (2ns rise time), the load is equivalent to a 0.123mH inductor followed by a 40pF capacitor to ground. Spice simulations show a peak current of 50mA lasting 6ns; at 40MHz, that is 6mA average current.