Here are the 3 procs
DynaPortDef: PUBLIC PROC [param: Parameter] RETURNS [ct: CellType] ~ {
Here is where the name and the size of public wires must be given
public: Wire ← CoreCreate.WireList[
LIST[
CoreCreate.Seq["prqlar",16],
CoreCreate.Seq["istatus",8],
CoreCreate.Seq["psendpar",15],
"psend",
CoreCreate.Seq["palpha",68],
CoreCreate.Seq["pbeta",68],
CoreCreate.Seq["pgama",68],
CoreCreate.Seq["pdelta",68],
CoreCreate.Seq["pepsilon",68],
CoreCreate.Seq["ialpha",68],
CoreCreate.Seq["ibeta",68],
CoreCreate.Seq["igama",68],
CoreCreate.Seq["idelta",68],
CoreCreate.Seq["iepsilon",68],
"pload",
"ickin"
]];
This creates a celltype
ct ← CoreClasses.CreateUnspecified[public: public];
This takes the parameter
CoreProperties.PutCellTypeProp[ct,$param,NEW[Parameter ← param]];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: dynaPort];
Now the type of each pins
Ports.InitPorts[ct, ls, drive,"prqlar"];
Ports.InitPorts[ct, ls, none,"istatus"];
Ports.InitPorts[ct, ls, drive,"psendpar"];
Ports.InitPorts[ct, l, drive,"psend"];
Ports.InitPorts[ct, ls, drive,"palpha"];
Ports.InitPorts[ct, ls, drive,"pbeta"];
Ports.InitPorts[ct, ls, drive,"pgama"];
Ports.InitPorts[ct, ls, drive,"pdelta"];
Ports.InitPorts[ct, ls, drive,"pepsilon"];
Ports.InitPorts[ct, ls, none,"ialpha"];
Ports.InitPorts[ct, ls, none,"ibeta"];
Ports.InitPorts[ct, ls, none,"igama"];
Ports.InitPorts[ct, ls, none,"idelta"];
Ports.InitPorts[ct, ls, none,"iepsilon"];
Ports.InitPorts[ct, l, drive,"pload"];
Ports.InitPorts[ct, l, none,"ickin"];
};
DynaPortInit:
PUBLIC Rosemary.InitProc = {
Init the state
--PROC [cellType: Core.CellType, p: Ports.Port, oldStateAny: REF ANY ← NIL] RETURNS [stateAny: REF ANY ← NIL]--
dynaport: DynaPortState ← IF oldStateAny=NIL THEN NEW[DynaPortRec] ELSE NARROW[oldStateAny, DynaPortState];
Create the pointers on different sequences
dynaport.rqlar ← NEW[Ports.LevelSequenceRec[16]];
dynaport.status ← NEW[Ports.LevelSequenceRec[8]];
dynaport.sendpar ← NEW[Ports.LevelSequenceRec[15]];
dynaport.alpha ← NEW[Ports.LevelSequenceRec[68]];
dynaport.beta ← NEW[Ports.LevelSequenceRec[68]];
dynaport.gama ← NEW[Ports.LevelSequenceRec[68]];
dynaport.delta ← NEW[Ports.LevelSequenceRec[68]];
dynaport.epsilon ← NEW[Ports.LevelSequenceRec[68]];
dynaport.ialpha ← NEW[Ports.LevelSequenceRec[68]];
dynaport.ibeta ← NEW[Ports.LevelSequenceRec[68]];
dynaport.igama ← NEW[Ports.LevelSequenceRec[68]];
dynaport.idelta ← NEW[Ports.LevelSequenceRec[68]];
dynaport.iepsilon ← NEW[Ports.LevelSequenceRec[68]];
Init the value
Ports.SetLS[dynaport.rqlar, X];
Ports.SetLS[dynaport.status, X];
Ports.SetLS[dynaport.sendpar, X];
Ports.SetLS[dynaport.alpha, X];
Ports.SetLS[dynaport.beta, X];
Ports.SetLS[dynaport.gama, X];
Ports.SetLS[dynaport.delta, X];
Ports.SetLS[dynaport.epsilon, X];
Ports.SetLS[dynaport.ialpha, X];
Ports.SetLS[dynaport.ibeta, X];
Ports.SetLS[dynaport.igama, X];
Ports.SetLS[dynaport.idelta, X];
Ports.SetLS[dynaport.iepsilon, X];
dynaport.send ← X;
dynaport.load ← X;
dynaport.ckin ← X;
Take the indice of each pins
[dynaport.RQLAR] ← Ports.PortIndexes[cellType.public,"prqlar"];
[dynaport.STATUS] ← Ports.PortIndexes[cellType.public,"istatus"];
[dynaport.SENDPAR] ← Ports.PortIndexes[cellType.public,"psendpar"];
[dynaport.SEND] ← Ports.PortIndexes[cellType.public,"psend"];
[dynaport.ALPHA] ← Ports.PortIndexes[cellType.public,"palpha"];
[dynaport.BETA] ← Ports.PortIndexes[cellType.public,"pbeta"];
[dynaport.GAMA] ← Ports.PortIndexes[cellType.public,"pgama"];
[dynaport.DELTA] ← Ports.PortIndexes[cellType.public,"pdelta"];
[dynaport.EPSILON] ← Ports.PortIndexes[cellType.public,"pepsilon"];
[dynaport.IALPHA] ← Ports.PortIndexes[cellType.public,"ialpha"];
[dynaport.IBETA] ← Ports.PortIndexes[cellType.public,"ibeta"];
[dynaport.IGAMA] ← Ports.PortIndexes[cellType.public,"igama"];
[dynaport.IDELTA] ← Ports.PortIndexes[cellType.public,"idelta"];
[dynaport.IEPSILON] ← Ports.PortIndexes[cellType.public,"iepsilon"];
[dynaport.LOAD] ← Ports.PortIndexes[cellType.public,"pload"];
[dynaport.CKIN] ← Ports.PortIndexes[cellType.public,"ickin"];
Take the parameter
dynaport.param ← NARROW[CoreProperties.GetCellTypeProp[cellType, $param], REF Parameter]^;
dynaport.countcycle ← 0;
dynaport.labelcycle ← 0; --is use for detecting edge of ckin
dynaport.testProcList ← NIL;
stateAny ← dynaport;
};
DynaPortEval:
PUBLIC Rosemary.EvalProc = {
--PROC [p: Ports.Port, stateAny: REF ANY, clockEval: BOOL]--
dynaport: DynaPortState ← NARROW[stateAny];
Assign the values of input pins to variables
dynaport.ckin ← p[dynaport.CKIN].l;
Ports.CopyLS[from: p[dynaport.STATUS].ls, to: dynaport.status];
Ports.CopyLS[from: p[dynaport.IALPHA].ls, to: dynaport.ialpha];
Ports.CopyLS[from: p[dynaport.IBETA].ls, to: dynaport.ibeta];
Ports.CopyLS[from: p[dynaport.IGAMA].ls, to: dynaport.igama];
Ports.CopyLS[from: p[dynaport.IDELTA].ls, to: dynaport.idelta];
Ports.CopyLS[from: p[dynaport.IEPSILON].ls, to: dynaport.iepsilon];
IF ~clockEval
AND dynaport.ckin=L
AND dynaport.labelcycle=1
THEN
dynaport.labelcycle ← 0; -- for detecting positive edge of ckin
IF ~clockEval
AND dynaport.ckin=H
AND dynaport
.labelcycle=0
THEN{
dynaport.labelcycle ← 1;
IF dynaport.param.ins ~= 0
THEN Simul2Sender.SendBus[dynaport]
ELSE {
-- default options on the Icon
Ports.LCToLS[dynaport.param.rqlar,dynaport.rqlar];
Ports.CToLS[0,dynaport.sendpar];
dynaport.send ← L;
Ports.LCToLS[dynaport.param.alpha[2],dynaport.alpha];
Ports.LCToLS[dynaport.param.beta[2],dynaport.beta];
Ports.LCToLS[dynaport.param.gama[2],dynaport.gama];
Ports.LCToLS[dynaport.param.delta[2],dynaport.delta];
Ports.LCToLS[dynaport.param.epsilon[2],dynaport.epsilon];
dynaport.countcycle ← IF dynaport.countcycle>5 THEN 6 ELSE dynaport.countcycle+1;
dynaport.load ← IF dynaport.countcycle>5 THEN L ELSE H
};
};
Ports.CopyLS[from: dynaport.rqlar, to: p[dynaport.RQLAR].ls];
Ports.CopyLS[from: dynaport.sendpar, to: p[dynaport.SENDPAR].ls];
p[dynaport.SEND].l ← dynaport.send;
Ports.CopyLS[from: dynaport.alpha, to: p[dynaport.ALPHA].ls];
Ports.CopyLS[from: dynaport.beta, to: p[dynaport.BETA].ls];
Ports.CopyLS[from: dynaport.gama, to: p[dynaport.GAMA].ls];
Ports.CopyLS[from: dynaport.delta, to: p[dynaport.DELTA].ls];
Ports.CopyLS[from: dynaport.epsilon, to: p[dynaport.EPSILON].ls];
p[dynaport.LOAD].l ← dynaport.load;
};
dynaPort: Core.ROPE = Rosemary.Register[roseClassName: "DynaPortDef", init: DynaPortInit, evalSimple: DynaPortEval, scheduleIfClockEval: TRUE];