DragonCMOSToolingSpecB.tioga
Hoel, January 28, 1987 12:29:36 pm PST
Hoel, August 16, 1986 4:54:49 pm PDT
DRAGON CMOS Tooling Specification
DRAGON CMOS Tooling Specification
DRAGON CMOS Tooling Specification
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
Dragon CMOS Tooling Specification
Jeff Hoel
Dragon-86-xx Written September 5, 1986 Revised January 28, 1987
© Copyright 1986 Xerox Corporation. All rights reserved.
Abstract: This document defines the requirements for tooling devices (masks) to be run using the current Dragon CMOS process.
Keywords: CMOS, Tooling Specification
FileName: /Indigo/Dragon/Documentation/DragonCMOSDesignRules/DragonCMOSToolingSpecB.tioga
XEROX  Xerox Corporation
   Palo Alto Research Center
   3333 Coyote Hill Road
   Palo Alto, California 94304



Dragon Project - For Internal Xerox Use Only
Contents
1. Description
2. Layout Grid
3. Drawn Layers
4. Mask Layers
5. Mask Alignment Sequence
6. Scribe Line
7. PCM Information
8. PE500 Alignment Key Information
9. Mask Ordering Information
ChangeLog
1. Description
This document defines the requirements for tooling devices (masks) to be run using the current Dragon CMOS process. At present, this is a 2.0 micron nwell CMOS process with two layers of metal, as defined in the Dragon CMOS Design Rules document [1]. The current foundry source is VLSI Technology Corporation (VTI). (Xerox PARC's Integrated Circuits Laboratory (ICL) is no longer in the foundry business.)
This document takes the approach that VTI's Tooling Specification [2] defines all requirements, except for those specified here. That is, this document will describe only the exceptions to VTI's Tooling Specification. (When we tried to do this for design rules, we eventually had to abandon the approach, and write a complete document. But this time maybe we can get away with it.)
We are currently using Revision *H of VTI's Tooling Specification. (For the first two VTI runs, we used Revision *C. For the third VTI run, we used Revision *E. All these specifications are very similar.)
For convenience, we adopt VTI's convention for numbering sections.
1.1 References
[1] Dragon CMOS Design Rules, Jeff Hoel,
/Indigo/Dragon/Documentation/DragonCMOSDesignRules/
DragonCMOSDesignRulesC.tioga, January 26, 1986.
[2] Tooling Specification for 2.0 Micron N-Well CMOS With Two Layers of Metal, Advanced Lithography Design Rules, 1x PE500/PE341 Lithography, Wes Erck, VTI document number 02-10001, Rev. *H, January 12, 1987.
2. Layout Grid
No exceptions. (All drawn shapes are on a 0.5-micron grid.)
3. Drawn Layers
The VTI document refers to some CIF layers they use to flag special cases. We don't use such layers, but it doesn't matter. There are no real exceptions.
4. Mask Layers
The VTI document lists the twelve mask layers to be constructed from the layout, and how they should be constructed. The following sections list our exceptions.
Note that the mask geometries constructed per Section 4. are subsequently biased according to Section 9. to make real masks. I think the general idea is that the results of Section 4. should be what you would have drawn if you were drawing what you expected to see on the wafer. (There are exceptions, of course. For example, the via construction is done to attempt to make vias drawn the same size turn out the same size on the wafer, whether they're over diffusion or not. The biasing specified in Section 9. is unable to bias different vias by different amounts.)
4.1. N-Well
There are two reasons why we must construct the Nwell mask in a non-standard way. First, our convention for drawing nwell differs from VTI's. Second, we have chosen a more agressive design rule for the minimum spacing permitted between p+ diffusion inside nwell and n+ diffusion outside nwell, and the placement of the nwell boundary must be acceptable to both VTI and ICL (see [1], rules 6.3.5., 6.3.7., and 6.3.12.). VTI has agreed to support this non-standard requirement. (1-28-87: Even though ICL is no longer a foundry source, we'll retain the non-standard derivation equation, for the other reasons cited.)
Nwell for the mask is constructed from "Dragon-drawn" nwell (i.e.., nwell drawn according to the Dragon convention, which is supported by the Chipndale layout system) by undersizing it by 1.0 microns per side, or 2000 nm diameter. In VTI's notation:
Mask Description  Derivation Equation  Denotch
26  N-well   D26 := CNW @ -1.0
VTI's standard derivation includes a CR layer, which they use for drawing nwell resistors. We don't use such resistors, nor do we have such a layer.
By the way, do we need any more formal citing of the agreement between PARC and VTI that permits us to do this non-standard thing?
The intent of this construction is to put the final electrical boundary between nwell and substrate at least 7 microns from p+ diffusions in nwell and at least 3 microns from n+ diffusions outside nwell. This "7-and-3" position is a compromise between VTI and ICL. VTI's standard requirement is "8-and-4." To meet our requirement for more aggressive spacing between p+ and n+, VTI first proposed "8-and-2," but this was not acceptable to ICL. ICL's standard requirement was "4-and-6," but they felt that anything between "3-and-7" and "7-and-3" would be acceptable. VTI then agreed to do "7-and-3." (1-28-87: Even though ICL is no longer a foundry source, we'll retain the non-standard derivation equation.)
4.2. P Field Dope
The construction of the P Field Dope mask is logically related to the construction of the Nwell mask, and is hence covered by the same agreement. It is constructed from "Dragon-drawn" nwell by oversizing it by 0.5 microns per side, or 1000 nm diameter. In VTI's notation:
Mask Description  Derivation Equation  Denotch
11  P field dope  D11 := CNW @ 0.5
Again, since we don't have a CR layer, it doesn't appear in our derivation equation. Also, we don't require a denotch threshold, since two constructed shapes can never become close enough to each other that merging them would be a good idea.
The objective is to assure that p field dope at least touches the nwell electrical boundary under a worst case misalignment of 1 micron. The nwell electrical boundary is 3 microns oversized from the nwell derived geometries, due to outdiffusion. (In other words, the nominal overlap of p field dope and electrical nwell is 1 micron.)
4.3. Via
Our derivation of the via mask differs from VTI's derivation, but we hope the differences are too minor to worry about. Both derivations oversize vias over diffusion, by 0.25 microns per side. But VTI oversizes only vias of minimum size, i.e., 2 x 2 microns.
Who  Derivation Equation       
VTI  D51 := (((area(CC2) <= 4.0) * D10) @ 0.25 + CC2
Us  D51 := (CC2 @ 0.25) * (D10 @ 0.25) + CC2
5. Mask Alignment Sequence
The VTI document specifies the alignment sequence VTI uses.
6. Scribe Line
We and VTI use different software systems to generate the scribe line geometries, but the results are intended to be more or less the same. It is beyond the scope of this document to describe exactly how our software works; but if such a document were written, we would reference it here.
6.2. Scribe Line Description
Our scribe line is constructed asymmetrically around the "user data" rectangle. All edges have a minimum amount of scribe line geometries. The left and bottom edges also have all of the rest of the scribe line area. This is done so that holes can be cut out of this scribe line "middle" area, and artifacts such as alignment keys and CD structures can be inserted. The precise location of these artifacts in the scribe line is not important.
(VTI's spec says its scribe line is 3-sided with the open end to the right. They also drop artifacts into the scribe line area.)
7. PCM Information
No exceptions.
8. PE500 Alignment Key Information
No exceptions.
9. Mask Ordering Information
The VTI document specifies that masks will be either 6 x 6 inches or 5 x 5 inches, at the option of the VTI Mask Tooling Group. But to remain mask compatible with ICL, we require them to be 5 x 5 inches. Since we don't have to be compatible with another foundry, we could consider either option, but for now the default will be 5 x 5 inches.
ChangeLog
Rev  Date  Description
--  9-5-86  Initial Release.
B  1-28-87  Conform to VTI's 02-10001, Rev *H.
      (Metal2 bias increased; Sec. 9)
      (Alignment key file format change; Sec. 8)
      VTI is now sole source; Sec. 1, 4.1, 5, 9