CLOCK GENERATOR DATASHEET CLOCK GENERATOR DATASHEET CLOCK GENERATOR DATASHEET 1 1 1 The DynaBus Clock Generator Ed Richley and Lissy Bland Dragon-88-07 May 1988 c Copyright 1988 Xerox Corporation. All rights reserved. Keywords: DynaBus clock, timing, clock skew, clock synchronization, clock phase adjustment; Maintained by: Bland.pa XEROX Xerox Corporation Palo Alto Research Center 3333 Coyote Hill Road Palo Alto, California 94304 For Internal Xerox Use Only The DynaBus Clock Generator 1.0 Brief Description The Clock Generator generates two synchronized CMOS-level clock signals from one differential ECL input. Each channel provides a clock signal for a slave chip on the DynaBus. The clock signal used by the slave chip is sensed by the clock generator chip and is used as feedback to minimize skew. Typical skew should be less than one nanosecond. 2.0 Pin-Out 3.0 Block Diagram of the Chip 4.0 Detailed Description of Each of the Functional Blocks 4.1 ECL Receiver The ECL Receiver receives an ECL-level reference signal from the clock distribution system. This reference signal is used as the standard in adjusting the phase of all clocks in the system. It is converted to CMOS levels by the ECL Receiver. 4.2 Phase Adjustment Unit The Phase Adjustment Unit minimizes clock skew between the reference signal and the CkOut signal. As Figure 1 indicates, a Phase Detector is used to perform phase comparison between the reference signal, and the clock signal from the slave chip (CkOutA). The value of ErrorOutA is used to correct for phase error. For example, if ErrorOutA is 1, less delay is needed and if ErrorOutA is 0, more delay is needed. The value of ErrorOutA is fed back to the VcA control line with a simple RC low pass filter to form a closed loop system that seeks minimum skew automatically. Using this system, clock skew should be less than 1 nanosecond. Figure 1: Adjusting clock skew: a simplified schematic. 4.3 Selecting A Value for RC The value of RC is dependent upon the operating frequency (cycle time) of the system. Because the value of ErrorOutA/ErrorOutB functions as a 1,000 ohm resistor wired in series with R, the calculation uses (R + 1000W)C. Experiments in the laboratory indicate that a practical solution is to set the value of (R + 1000W)C to 5000 times the cycle time, so that: (R + 1000W)C = 5000 Tcycle Where Tcycle is the clock cycle time. This means for a system with a cycle time of 25 nanoseconds, (R + 1000W)C should be at least 12.5 microseconds. The duration of the nResetA/nResetB signals, Treset, is set in relation to the value of (R + 1000W)C. In general, it should be 5 times that value, so that: Treset = 5(R + 1000W)C. 5.0 Detailed Description of Each Pin Pin Name I/O Pin Description nResetA/nResetB I A negative pulse supplied during start-up to initialize the circuit to a known state so that the circuitry can determine the least correction necessary to adjust the phase of the clock signals. The duration of nResetA/nResetB should be at least (5 * (R + 1K Ohms)*C). It is a 5 volt signal. ECLIn/nECLIn I A pair of signals that are the reference signal from the clock generator. Delivered as a differential positive supply ECL. Low ~ 3 volts, high ~ 4 volts. nLockedA/nLockedB O When asserted, nLockedA/nLockedB indicates that the phase adjustment mechanism for clock signals is functioning correctly. ErrorOutA/ErrorOutB O The output Phase Detector. If the ouput is one, the phase is late. If zero, the phase is early. VcA/VcB I A control voltage that adjusts the phase of the clock that goes to the slave circuit. ClockA/ClockB O The clock signal that is sent to DynaBus slaveChipA and slaveChipB, respectively. CkOutA/CkOutB I The clock signal that is actually used DynaBus slaveChipA and slaveChipB, respectively. 6.0 DC Characteristics Pin Name Signal Type Voltage Current nResetA/nResetB 5V Input L 0.5 H 4.5 nLockedA/nLockedB 5V Output L 0.5 +12 mA H 4.0 -12 mA ECLIn ECL Input L 3.0 H 4.0 nECLIn ECL Input L 3.0 +6.8 mA H 4.0 +6.8 mA ClockA/ClockB 5V Output L 0.5 +96 mA H 4.0 -96 mA CKOutA/CkOutB 5V Input L 0.5 H 4.5 ErrorOutA/ErrorOutB 5V Output L 0.5 +1.5 mA H 4.0 -1.5 mA VcA/VcB 5V Input L 0.5 H 4.5 7.0. AC Characteristics A. Definitions The timing characteristic of each port are described in this section. It is generally assumed that the charcteristics of all the wires connecting a chip to a particular component are the same, so that Dynabus signals, DBug Bus signals, Backpanel signals, (etc.) may be characterized as a group. Figure 4: Input Signal Characteristics Ts (setup time) = the mimimum time a signal must be stable before the rising edge of the clock. Th (hold time) = the mimimum time a signal must be stable after the rising edge of the clock. Figure 5: Output Signal Characteristics Tcycle = the time interval between successive rising edges of the clock Tpd (propagation delay) = the waiting time after the clock is high until an output becomes valid. Tm (maintenance of old data) = the time after rising edge of next clock cycle that old data remains valid. B. Values Qualififed Pin Name Tmin Ttypical Tmax Tcycle    Ts.Dynabus In (setup.Dynabus In)    Th.Dynabus In (hold.Dynabus In)    Tpd.Dynabus Out (propagation delay.Dynabus Out) Tm.Dynabus Out (maintain.Dynabus Out) 8.0 Application Schematics of the Circuit 9.0 Physical Pin-Out For Each Package Num Name Num Name 1 ClockA 9 VcB 2 CkOutA 10 nLockedB 3 nECLIn 11 ErrorOutB 4 nResetA 12 nResetB 5 ErrorOutA 13 ECLIn 6 nLockedA 14 CkOutB 7 VcA 15 ClockB 8 Gnd 16 Vdd  [Artwork node; type 'Artwork on' to command tool] [Artwork node; type 'Artwork on' to command tool] [Artwork node; type 'Artwork on' to command tool] [Artwork node; type 'Artwork on' to command tool] [Artwork node; type 'Artwork on' to command tool] artworkFigureartworkFigure [Artwork node; type 'Artwork on' to command tool] [Artwork node; type 'Artwork on' to command tool] ʶ"dragondoc" style.8 in footerMarginIblockMark centerHeaders KcenterRectoHeader KcenterVersoHeader Ke"XeroxLogotypes" family 48 pt size 48 pt leading 48 pt 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