The following table describes the PC/AT pins of the IOBridge. Unless otherwise specified, those pins use little endian bit-ordering (bit 0 is LSB).
Pin Name I/O Pin Description
PCLK I PC/AT bus clock. This clock is used to derive the timings on the PC/AT bus when the IOBridge is the bus master.
Reset I PC/AT bus reset. This signal resets the internal PC/AT related automata. It should always be asserted together with the DBus DReset and should be rescinded before it.
BAck I Acknowledge of PC/AT bus allocation. Asserted by PC/AT bus allocator after BReq has been asserted by the IOBridge. Signal should not be rescinded before BReq is rescinded.
BReq I Allocation request for PC/AT bus.
nFault I/O Input when IOBridge is PC/AT bus master (BAck high), output when IOBridge is PC/AT bus slave. When the IOBridge is master, the DynaBus transaction will return in error if nFault is asserted at the end of the PC/AT cycle. When the IOBridge is slave, nFault will be asserted if the request cannot be completed properly (DynaBus error detected by the cache).
nWRXnIOW I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When the IOBridge is PC/AT bus master, nWRXnIOW is asserted to indicate an IOWrite cycle on the PC/AT bus. When the IOBridge is PC/AT bus slave, nWRXnIOW asserted means that an extended address memory write cycle is active (as nWRX, except that 32 bit addresses are used and nMemCS/nIOCS are ignored)
nRDXnIOR I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When the IOBridge is PC/AT bus master, nRDXnIOR is asserted to indicate an IORead cycle on the PC/AT bus. When the IOBridge is PC/AT bus slave, nRDXnIOR asserted means that an extended address memory read cycle is active (as nRDX, except that 32 bit addresses are used and nMemCS/nIOCS are ignored)
nReady I/O Input when IOBridge is PC/AT bus master, output when IOBridge is PC/AT bus slave. When the IOBridge is PC/AT bus master, nReady prevents completion of the PC/AT bus cycle as long as it is active. When the IOBridge is PC/AT bus slave, nReady is asserted as long as the IOBridge has not provided/sampled the data on the PC/AT bus.
nIOCS I When active (low), indicates that nWR/nRD cycle is for access to IOBridge registers.
nMemCS I When active (low), indicates that nWR/nRD cycle is for access to DynaBus memory.
nWR I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When the IOBridge is PC/AT bus master, nWR is asserted to indicate a memory write cycle on the PC/AT bus. When the IOBridge is PC/AT bus slave, nWR asserted means that a write cycle is active. The cycle is ignored if neither nMemCS or nIOCS is active.
nRD I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When the IOBridge is PC/AT bus master, nRD is asserted to indicate a memory read cycle on the PC/AT bus. When the IOBridge is PC/AT bus slave, nWR asserted means that a read cycle is active. The cycle is ignored if neither nMemCS nor nIOCS is active.
nBHE I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. Indicates that data high order byte takes part in transaction (when low).
A31nDEN I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When IOBridge is PC/AT bus master, asserted (low) when data transceivers should be enabled. When IOBridge is PC/AT bus slave, this signal is the extended address bit 31 (msb).
A30DTnR I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When IOBridge is PC/AT bus master, asserted (low) when data transceivers should transmit towards the IOBridge. When IOBridge is PC/AT bus slave, this signal is the extended address bit 30 (next to msb).
A29nINTA I/O Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. When IOBridge is PC/AT bus master, asserted (low) to acknowledge PC/AT bus interrupt when using 8259 interrupt controllers. When IOBridge is PC/AT bus slave, this signal is the extended address bit 29.
A28-A24 I 5 bits, extended address bits 28 to 24.
Address I/O 24 bits. Input when IOBridge is PC/AT bus slave, output when IOBridge is PC/AT bus master. Full PC/AT bus address.
DATA I/O 16 bits. Direction defined by master/slave and read/write in the obvious fashion. Represents the data bus of the PC/AT.
IntOut O Driven when the DynaBus requests an interrupt on the PC/AT bus.
INTR I Driven to indicate that an interrupt should be passed on to the DynaBus. Logical acknowledge provided by A29nINTA.