DIRECTORY Basics, BitmapViewer, Commander, CRIO, ImagerSample, ICTest, IO, Process, Rope, ViewerClasses, ViewerOps; CRTest: CEDAR PROGRAM IMPORTS Basics, BitmapViewer, Commander, CRIO, ImagerSample, ICTest, IO, Process, ViewerOps = BEGIN Address: TYPE = [0..2048); size: INT; DataIndex: TYPE = [0..32); LastRow: INT = 255; LastColumn: INT = 255; rectangle: ImagerSample.Box = [[0, 0], [LastColumn+1, LastRow+1]]; dataViewer: ViewerClasses.Viewer; dataBitmap: ImagerSample.SampleMap; errorViewer: ViewerClasses.Viewer; errorBitmap: ImagerSample.SampleMap; Viewer: TYPE = ViewerClasses.Viewer; ROPE: TYPE = Rope.ROPE; errorBitMap: ROPE _ "CrossRAM Error Bit Map"; dataBitMap: ROPE _ "CrossRAM Data Bit Map"; cr02: BOOL _ FALSE; cr03: BOOL _ FALSE; dataDisplay: BOOL _ FALSE; noRefresh: BOOL _ FALSE; bigChip: BOOL _ FALSE; Ram: TYPE = ARRAY [0..2048) OF LONG CARDINAL; ram: REF Ram; h: ICTest.Handle _ NIL; Init: PROC RETURNS [ok: BOOL] = { IF (cr02 AND cr03) OR (NOT cr02 AND NOT cr03) THEN { IO.PutF[h.viewerout, "Select one chip type\n"]; RETURN[FALSE]; }; size _ SELECT TRUE FROM cr02 => 1920, -- 60*4*8 -- cr03 => 1856, -- 58*4*8 -- ENDCASE => 0; IF dataDisplay AND (dataViewer _ ViewerOps.FindViewer[dataBitMap]) = NIL THEN { dataViewer _ BitmapViewer.Create[info: [name: dataBitMap]]; dataBitmap _ ImagerSample.NewSampleMap[rectangle]; BitmapViewer.SetBitmap[dataViewer, dataBitmap]; ImagerSample.Clear[dataBitmap]; }; IF (errorViewer _ ViewerOps.FindViewer[errorBitMap]) = NIL THEN { errorViewer _ BitmapViewer.Create[info: [name: errorBitMap]]; errorBitmap _ ImagerSample.NewSampleMap[rectangle]; BitmapViewer.SetBitmap[errorViewer, errorBitmap]; }; ImagerSample.Clear[errorBitmap]; IF NOT h.enableTester AND ram=NIL THEN ram _ NEW[Ram]; IF errorViewer.iconic THEN ViewerOps.OpenIcon[icon: errorViewer]; ViewerOps.ChangeColumn[viewer: errorViewer, newColumn: left]; ViewerOps.BottomViewer[viewer: errorViewer]; RETURN[TRUE]; }; NoRefresh: ICTest.ControlProc = { noRefresh _ control; }; TesterOn: PROC [] = { IF h.enableTester THEN { CRIO.Init[bigChip: bigChip]; CRIO.EmergencyRefresh[on: NOT noRefresh]; CRIO.Test[on: TRUE]; Process.Pause[Process.MsecToTicks[500]]; } ; }; TesterOff: PROC [] = { IF h.enableTester THEN { CRIO.Test[on: FALSE]; Process.Pause[Process.MsecToTicks[500]]; }; }; DataDisplay: ICTest.ControlProc = { dataDisplay _ control; }; CrossRAM02: ICTest.ControlProc = { cr02 _ control; }; CrossRAM03: ICTest.ControlProc = { cr03 _ control; }; SimpleTest: ICTest.TestProc = { IF NOT Init[] THEN RETURN; TesterOn[]; FOR i: INT IN [0..size) DO CycleRAM[i, 0, TRUE]; CycleRAM[i, 0, FALSE]; CycleRAM[i, 0FFFFFFFFh, TRUE]; CycleRAM[i, 0FFFFFFFFh, FALSE]; ICTest.CheckStop[h]; ENDLOOP; Refresh[]; TesterOff[]; }; LoopTest: ICTest.TestProc = { Loop: PROC [] = { DO CycleRAM[02AAH, 0AAAAAAAAH, TRUE]; CycleRAM[0555H, 55555555H, TRUE]; CycleRAM[02AAH, 0AAAAAAAAH, FALSE]; CycleRAM[0555H, 55555555H, FALSE]; ICTest.CheckStop[h]; ENDLOOP; }; IF NOT Init[] THEN RETURN; TesterOn[]; Loop[! ICTest.AbortDieSignal => TesterOff[]]; TesterOff[]; }; AddressTest: ICTest.TestProc = { IF NOT Init[] THEN RETURN; TesterOn[]; FOR i: INT IN [0..size) DO CycleRAM[i, i, TRUE]; ICTest.CheckStop[h]; ENDLOOP; Refresh[]; FOR i: INT IN [0..size) DO CycleRAM[i, i, FALSE]; ICTest.CheckStop[h]; ENDLOOP; Refresh[]; TesterOff[]; }; IllinoisTest: ICTest.TestProc = { StepIndex: TYPE = [0..8); complementUpper: ARRAY StepIndex OF BOOL = [TRUE,TRUE,FALSE,TRUE,FALSE,FALSE,TRUE,FALSE]; writeData: ARRAY StepIndex OF BOOL = [TRUE,FALSE,TRUE,TRUE,FALSE,TRUE,FALSE,FALSE]; readData: ARRAY StepIndex OF BOOL = [FALSE,FALSE,FALSE,TRUE,TRUE,TRUE,TRUE,FALSE]; halfBit: INT _ LAST[Address]+1; IF NOT Init[] THEN RETURN; TesterOn[]; FOR address: INT IN [0..size) DO CycleRAM[address, 0, TRUE]; ENDLOOP; UNTIL (halfBit _ halfBit/2) = 4 DO FOR step: StepIndex IN StepIndex DO HalfStep[upper: complementUpper[step], data: writeData[step], write: TRUE, halfbit: halfBit]; HalfStep[upper: NOT complementUpper[step], data: readData[step], write: FALSE, halfbit: halfBit]; Refresh[]; ICTest.CheckStop[h]; ENDLOOP; ENDLOOP; TesterOff[]; }; HalfStep: PROC [upper: BOOL, data: BOOL, write: BOOL, halfbit: INT] = { address: CARDINAL _ IF upper THEN halfbit ELSE 0; addressMod: CARDINAL; DO CycleRAM[address, IF data THEN 0FFFFFFFFH ELSE 0, write]; address _ address + 1; addressMod _ address MOD (2*halfbit); IF (upper AND addressMod=0) OR (NOT upper AND addressMod=halfbit) THEN address _ address + halfbit; IF address>=size THEN EXIT; ENDLOOP; }; CycleRAM: PROC [address: Address, data: LONG CARDINAL, write: BOOL] = { ramAdd: Address; SELECT TRUE FROM cr02 => { address _ address + 128; ramAdd _ address; }; cr03 => { address _ address + 192; ramAdd _ Basics.BITAND[address, 07h]; ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 100h]#0 THEN 008h ELSE 0]; ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 200h]#0 THEN 010h ELSE 0]; ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 040h]#0 THEN 020h ELSE 0]; ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 080h]#0 THEN 040h ELSE 0]; ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 010h]#0 THEN 080h ELSE 0]; ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 020h]#0 THEN 100h ELSE 0]; ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 400h]#0 THEN 200h ELSE 0]; ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 008h]#0 THEN 400h ELSE 0]; ramAdd _ Basics.BITXOR[ramAdd, 7f0h]; }; ENDCASE => ERROR; IF write THEN { word: CARDINAL; IF h.enableTester THEN CRIO.CRWrite[ramAdd, data] ELSE ram[address] _ data; IF dataDisplay THEN { word _ Basics.HighHalf[data]; IF bigChip THEN FOR bit: CARDINAL IN [0..16) DO PutBit[dataBitmap, address, bit, Basics.BITAND[word, 8000H] # 0]; word _ word*2; ENDLOOP; word _ Basics.LowHalf[data]; FOR bit: CARDINAL IN [IF bigChip THEN 0 ELSE 1..16) DO PutBit[dataBitmap, address, bit+16, Basics.BITAND[word, IF bigChip THEN 8000H ELSE 4000H] # 0]; word _ word*2; ENDLOOP; }; } ELSE { readData: LONG CARDINAL _ data; word: CARDINAL; IF h.enableTester THEN readData _ CRIO.CRRead[ramAdd] ELSE readData _ ram[address]; IF readData#data THEN { word _ Basics.BITXOR[Basics.HighHalf[readData], Basics.HighHalf[data]]; IF bigChip THEN FOR bit: CARDINAL IN [0..16) DO IF Basics.BITAND[word, 8000H] # 0 THEN PutBit[errorBitmap, address, bit, TRUE]; word _ word*2; ENDLOOP; word _ Basics.BITXOR[Basics.LowHalf[readData], Basics.LowHalf[data]]; FOR bit: CARDINAL IN [IF bigChip THEN 0 ELSE 1..16) DO IF Basics.BITAND[word, 8000H] # 0 THEN PutBit[errorBitmap, address, bit+16, TRUE]; word _ word*2; ENDLOOP; }; }; }; PutBit: PROC [bitmap: ImagerSample.SampleMap, address: Address, bit: DataIndex, data: BOOL] = { slow: INTEGER _ LastRow - (address/8); fast: INTEGER _ LastColumn - (bit*8 + 7 - (address MOD 8)); ImagerSample.Put[bitmap, [slow, fast], IF data THEN 0FFFFh ELSE 0]; }; Refresh: PROC = { IF dataDisplay THEN BitmapViewer.TouchUp[dataViewer, rectangle]; BitmapViewer.TouchUp[errorViewer, rectangle]; }; MakeCRTestTool: Commander.CommandProc = { h _ ICTest.MakeICTestTool["Testing CrossRAM", 5]; ICTest.PutUpTestButton["Illinois Test", IllinoisTest, h]; ICTest.PutUpTestButton["Simple Test", SimpleTest, h]; ICTest.PutUpTestButton["Loop Test", LoopTest, h]; ICTest.PutUpTestButton["Address Test", AddressTest, h]; ICTest.PutUpControlButton["CrossRAM02", CrossRAM02, h, TRUE]; ICTest.PutUpControlButton["CrossRAM03", CrossRAM03, h, FALSE]; ICTest.PutUpControlButton["Data Display", DataDisplay, h, FALSE]; ICTest.PutUpControlButton["No Refresh", NoRefresh, h, FALSE]; }; Commander.Register[key: "CRTest", proc: MakeCRTestTool, doc: "Create a tool for testing CrossRAMs" ]; END. вCRTest.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Last Edited by: Gasbarro April 23, 1986 10:33:40 am PST Gunther, November 4, 1985 3:27:24 pm PST Barth, September 27, 1985 5:28:19 pm PDT write zero to all locations divide RAM by columns instead of rows the low order bits address left to right the high order bits address from top to bottom the data bits are in order from right to left Э╩ЎШcodeЪЬЩKЪЬ ╧mЬ1ЩJЪЬ:ЮЬШAJЪЬ6ЮЬШ=JЪЬШJШЧЪЬ7Ш7JЪЬ-Ш-ЧJШJЪЮЬШЧЕЧ$+╝