<> <> <> <<>> <<-- Start everything and read in the source design>> Statistics on -- you always want to know how long it took ColorDisplayModeOff -- saves a lot of cycles Install DAUser SCCmosB PadFrame _ CedarProcess.SetPriority[background] _ &design _ PW.OpenDesign["ClockGen.dale"] -- read the CD design _ &cx _ Sisyph.Create[&design, NIL] -- this creates a context for Sysiph <<-- Extract cell>> _ &ct _ Sisyph.ES["ClockGen.sch", &cx] -- this extracts the top-level schematic <<-- Generate Layout>> _ &ob _ PWCore.Layout[&ct] _ PW.Draw[&ob] _ PWCore.Store[&ct, TRUE] <<>> <<-- Apply Static to find unconnected wires>> Install Static _ Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]] <<-- errors can be found found in the terminal>> <<-- Compare layout and schematics>> Install PWCoreLichen _ PWCoreLichen.SetAutomorphismHack[TRUE] _ PWCoreLichen.CompareForTheRestOfUs[&ct, &design, 0.8] <<>> <<-- Check the connectivity>> Install ConnectivityChecker CheckConnectivity ClockGenLayout.dale <<-- signals all disconnected internals; returns a list of disconnected publics>> <<>> <<-- DRC ClockGenLayout.dale (we need a programming interface)>> <<>>