Presentation of BIC Early 1988 1 Bus Interface Chip: BIC Decouples electrically the hybrid from the bus Bit-sliced bidirectionnal register (24 bits) Fast low-voltage drivers and receivers Clock distribution and skew control Reduces number of bus taps DBus amplification and decoding, ... Working prototype since August 1987 Block Diagram Pinout Mounted in a large PGA (cavity size) Power: +5V, Gnd, separate Gnd for high-speed bus Bias voltages: for data and clock 2V receivers Clocks: 7 clock-related wires Debug bus: DBus (8), DCS, DOEn, Name DBus amplification: 3 pairs Arbiter: 4 Grant wires and SStop Dynabus: 24 data (I/O), 2 requests, 1 Or4 Hybrid bus: 24 data (I/O), 2 requests, 4 Or4 Bit Slice Data in hybrid: two mono-directional buses Data: 24 bits, bidir., grant, scan path Request: 2 bits, out only, no grant, scan path Or4: 1 bit, out only, no grant, no scan path Hybrid layout explains the aspect ratio of BIC Standard pad frame for slaves Grant Arbiter issues separate grants for slaves Debug Bus Asynchronous bus Hybrid select -> chip select Address (access to address register) Reset, Freeze, Shift, Execute (step-by-step) DBusIn, DBusOut Scan paths Chip ID [16]: pattern[4], type[6], version[6] Data path [52]: Internal Clock Skew register [4] External Clock Skew register [4] DBus distribution Decoding DBus address register -> Chip Select 2 bits -> BIC itself + 3 slaves Up to 12 slaves possible Clock Distribution Reference clock is carefully distributed BIC adjusts its clock and one slave's clock Adjustment done through DBus at power-up Skew control Completely digital logic; two copies / BIC Maximum allowable skew: 1.7 ns Variations on clock load, buffer size, temperature, supply voltage, processing Processing variation is dominant 16 taps, 0.7ns increment Layout Generation Layout through schematics annotations Complete description by schematics High-power latchup-resistant cells for drivers DIrect connection from/to pads Large transistors Standard cells for control Status First design Feb-May 1987, R. Bruce and L. Monier (part-time) Style: large high-power SC + regular SC Status of BIC1 Tested August 1987 100% functional yield >> 50% used on hybrid prototypes expected 15ns min period on hybrid Second design Specs drifted a tad Submitted December 1987 n[Artwork node; type 'ArtworkInterpress on' to command tool] [Artwork node; type 'ArtworkInterpress on' to command tool] [Artwork node; type 'ArtworkInterpress on' to command tool] [Artwork node; type 'ArtworkInterpress on' to command tool] [Artwork node; type 'ArtworkInterpress on' to command tool] [Artwork node; type 'ArtworkInterpress on' to command tool] _"slides" style#PressFonts 1000.0 firstVisibleFolioIunleadedMark insideFooterdisK outsideFooter Iblock centerFootere"XeroxLogotypes" family 48 pt size 48 pt leading 48 pt topLeading 40 pt topIndent 24 pt bottomLeadingtitleIraggedNb..N..N((N%%NN&&N%% NNI artworkFigureFitTRUE Interpress+Interpress/Xerox/3.0 fjXeroxResearchCMYKXerox PressFonts Helvetica-MRRXerox PressFonts Helvetica-MRRXerox PressFonts Helvetica-MRRkj蠤F񠤠h 2xjb04PT 04`bbb220044d¡`ġ4dġ0ġddġbdb`d`dddddd¡ġġġġRRPPġPPTT220044    D@4D 0DD4t4t44Tt4Pttddldldddbb```````ddd`dbdb`0`4`d``dd`dd`dddjjdhhhhdhdldllhlBdB@d@DdDddhhlld`d```dddbdb`d`dddD@DDDBdB@d@DdDdddbDb```````0`4`D``dd@dD`Dd`bb````````dddd`dbDb```` `0`4`D``dd@dD`Dda"a`"```````b"b2"2`0"0`4"4`"`"`"`"`"`"`"`"`"`"`"`"`2"2`0"0`4"4` " `"` " `"`"`"`"h"h`h"`R"RlP"P`P`PlPlTlThTlT"Th"`"`"`"`"`"`2"2`0"0`4"4`""`ġ"`!b! b  "4"`""0"""""""4"" "0"""""T"""P"""4"""0"b b"kxj0 amplifiers  2P6DBus  Data P 4Clocks BDCS( BDBus0 26 Reference |Bus side (low-voltage) ĠHybrid side (5V CMOS levels) @ HFP™ 𠢠T™T@ @F(JJ  8F(ʠ DBus( ~decoder8  Clock ~ amplifiers  F(ꠢFJJ @ x @`h ؠ @ Fꠢ @ 0(@ @ `H3 h™ h™F xv3 ʠ24 @ 1 @ 2 h h ؠh ؠ`Request 2Clocks 2@ x^Shared H ⠢6Owner H SStop H 2Grant BkkgArtwork InterpressBounds810.0 mm xmin 10.0 mm ymin 205.9 mm xmax 123.1676 mm ymax0.5776805 the lineLength .mul 2.811678 .add topLeading 0.5776805 the lineLength .mul 2.811678 .add topIndent 1.405839 mm bottomLeadingn;;N$$N22N11NN&&NN##N++N.. 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