<> <> <> << >> <> << >> <<>> <> <> <> <> << >> <> << >> <<>> <> <> <> <> <> << >> <> << >> <<>> <<-- Start everything and read in the source design>> Statistics on -- you always want to know how long it took ColorDisplayModeOff -- saves a lot of cycles Install DAUser SC PadFrame <<-- and anything else you might need such as FSA, DP, Alps, ..., or any of your private code>> _ CedarProcess.SetPriority[background] CDRead BIC.dale _ &design _ CDViewer.FindDesign["BIC"] -- read the CD design _ &cx _ Sisyph.Create[&design, NIL] -- this creates a context for Sysiph <<-- Generate celltype: the top-level schematic is read and extracted>> _ &ct _ Sisyph.ES["BIC.sch", &cx] -- this extracts the top-level schematic <<-- Apply Static>> Install Static _ Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]] <<-- errors can be found found in the terminal>> <<>> <<-- Generate Layout>> _ &ob _ PWCore.Layout[&ct] <<-- creates the CD object and attaches it to the cellType>> _ PW.Draw[&ob] <<-- just a viewer; don't edit or save it>> _ PWCore.Store[&ct, TRUE] <<-- saves the decorated Core under BIC.core, the layout under BICLayout.dale, and a view of the public pins under BICShell.dale>> <<-- the decorated Core will be read back for future work>> <<-- the layout will be DRCed, plotted, and turned into a Mebes file>> <<-- the shell will be needed to check the pad position and make the probing and bonding maps>> <<-- If your design is too large and must be done in several VMs, the trick is to produce decorated Core files from schematic for large blocks, and have the corresponding icons read the Core file instead of extracting the schematic. The receipe for making the decorated Core files is described above. The icon should be created by >> <> <<-- If the construction fits in one VM, it is better to remove intermediate checkpoints for final constructions.>> <<>> <<-- Compare layout and schematics>> Install PWCoreLichen _ PWCoreLichen.SetAutomorphismHack[TRUE] _ PWCoreLichen.CompareForTheRestOfUs[&ct, &design, 0.8] <<-- compares the cellType with the extracted layout>> <<>> <<-- Apply MintCheck>> Install Mint _ &circuit _ Mint.CreateCircuit[&ct] _ MintCmds.PrepareCircuit[&circuit, FALSE]; _ Mint.CheckLibrary[&circuit] <<-- errors can be found found in the terminal>> <<-- make a note of this number of transistors, and write home about it>> <<-- you also get an estimation of the total capacitance which you can use to derive an upper bound on the average power consumption.>> <<>> <<-- Check the connectivity>> Install ConnectivityChecker CheckConnectivity BICLayout.dale -- signals all disconnected internals; returns a list of disconnected publics; -- also checks for shorts in routing cells _ RoutingCheck.CheckObject[&ob] <<-- Simulate as completely as possible, at transistor level (assuming oracle)>> <<_ &oracle _ Sisyph.ES["BICTransistorLevel.sim", &cx]>> <<-- this extracts the schematics containing the top-level cell with its oracle (assuming same design)>> <<-- use the "log" parameter on the oracle>> <<-- put an object property "Simulation: $Transistors" inside BICTransistorLevel.sim to be sure to simulate at transistor level; if you stay at gate level for example, your blind faith in Logic might cost you a lot.>> <<-- when simulating at transistor level, use a separate clock for the circuit and the oracle: up_2 and dn_2 on both, but firstEdge _ 2 on the circuit clock works well and preserves the oracle file.>> <<_ &tester _ Logic.RunRosemary[&oracle, &design]>> <<_ RosemaryUser.StartTest[&tester]>> <<-- batch mode for oracle>> <> <<-- the log of all bugs found during the simulation; if empty, no bugs>> <<>> <<-- Simulate as completely as possible, at transistor level (assuming testproc)>> <> <<>> <<>> <<-- DRC BICLayout.dale (we need a programming interface)>> <<>> <<-- Plots>> <> <<-- Plot BICLayout.dale and eyeball it>> <<>> <<-- Use the shell to produce a bonding map; make sure that all bonding and wiring constraints are satisfied>> <<>> <<-- Generate the Mebes files>> <> <<_ %CDMEBES.stripesPerClump _ 5;>> <<_ %CDMEBES.wDir _ "///mebes/">> <<_ &design _ PW.OpenDesign["BICLayout"]>> <<_ CDProperties.PutDesignProp[&design, $CDMEBESMaskSetName, "BIC56789"]>> <<-- 9 chars, alphanum>> <<_ CDMEBESMainImpl.StartMEBESMask[NEW[CDSequencer.CommandRec _ [design: &design]]]>> <<-- generates a bunch of files of the form BIC56789.AAA>> <<>> <<-- Smodel under /indigo/dragon7.0/BIC12Oct87.df and archive immediately>> <<>> <<-- Visit your travel agent for good prices for Tahiti>>