Copyright 1987 by Xerox Corporation. All rights reserved.
Louis Monier June 29, 1988 3:18:12 pm PDT
This command file captures all the operations necessary to "finish" a circuit before fabrication. It has been tried on BIC, and gathers a lot of relevant information from all over the DA system.
Each designer is advised to make a copy and customize it.
Disclaimer: Using this command file does not prevent you from reading all about all tools and make any relevant choice of different or extra steps.
The file can be broken into separate files chained by RollBackAnd if you run out of resources on your machine (you will). You then have to duplicate some of the steps (read design, ...)
All libraries have been run through the DRC and Lichen (standard cells, pads, ram) and are frozen until the run goes out.
The design is completed, has been simulated at transistor level, and some timing estimation made (Mint, Spice...)
For power bus sizing, eyeball and be conservative.
You have a df file pertaining to this chip; the df file must verify, so that you can switch between machines rapidly.
You keep a daily log of your work on the chip (very useful when testing the wafers).
The command file
-- Start everything and read in the source design
Statistics on
-- you always want to know how long it took
-- saves a lot of cycles
Install DAUser SC PadFrame
-- and anything else you might need such as FSA, DP, Alps, ..., or any of your private code
← CedarProcess.SetPriority[background]
CDRead BIC.dale
← &design ← CDViewer.FindDesign["BIC"]
-- read the CD design
← &cx ← Sisyph.Create[&design, NIL]   
-- this creates a context for Sysiph
-- Generate celltype: the top-level schematic is read and extracted
← &ct ← Sisyph.ES["BIC.sch", &cx]
-- this extracts the top-level schematic
-- Apply Static
Install Static
← Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]]
-- errors can be found found in the terminal
-- Generate Layout
← &ob ← PWCore.Layout[&ct]
-- creates the CD object and attaches it to the cellType
← PW.Draw[&ob]
-- just a viewer; don't edit or save it
← PWCore.Store[&ct, TRUE]  
-- saves the decorated Core under BIC.core, the layout under BICLayout.dale, and a view of the public pins under BICShell.dale
-- the decorated Core will be read back for future work
-- the layout will be DRCed, plotted, and turned into a Mebes file
-- the shell will be needed to check the pad position and make the probing and bonding maps
-- If your design is too large and must be done in several VMs, the trick is to produce decorated Core files from schematic for large blocks, and have the corresponding icons read the Core file instead of extracting the schematic. The receipe for making the decorated Core files is described above. The icon should be created by
SPACE-O/make cell icon/from code/PWCore.Retrieve["CHIP"].
-- If the construction fits in one VM, it is better to remove intermediate checkpoints for final constructions.
-- Compare layout and schematics
Install PWCoreLichen
← PWCoreLichen.SetAutomorphismHack[TRUE]
← PWCoreLichen.CompareForTheRestOfUs[&ct, &design, 0.8]
-- compares the cellType with the extracted layout
-- Apply MintCheck
Install Mint
← &circuit ← Mint.CreateCircuit[&ct]
← MintCmds.PrepareCircuit[&circuit, FALSE];
← Mint.CheckLibrary[&circuit]
-- errors can be found found in the terminal
-- make a note of this number of transistors, and write home about it
-- you also get an estimation of the total capacitance which you can use to derive an upper bound on the average power consumption.
-- Check the connectivity
Install ConnectivityChecker
CheckConnectivity BICLayout.dale
-- signals all disconnected internals; returns a list of disconnected publics;
-- also checks for shorts in routing cells
← RoutingCheck.CheckObject[&ob]
-- Simulate as completely as possible, at transistor level (assuming oracle)
← &oracle ← Sisyph.ES["BICTransistorLevel.sim", &cx]
-- this extracts the schematics containing the top-level cell with its oracle (assuming same design)
-- use the "log" parameter on the oracle
-- put an object property "Simulation: $Transistors" inside BICTransistorLevel.sim to be sure to simulate at transistor level; if you stay at gate level for example, your blind faith in Logic might cost you a lot.
-- when simulating at transistor level, use a separate clock for the circuit and the oracle: up𡤂 and dn𡤂 on both, but firstEdge ← 2 on the circuit clock works well and preserves the oracle file.
← &tester ← Logic.RunRosemary[&oracle, &design]
← RosemaryUser.StartTest[&tester]
-- batch mode for oracle
open ///Temp/InterfaceChip.bugs
-- the log of all bugs found during the simulation; if empty, no bugs
-- Simulate as completely as possible, at transistor level (assuming testproc)
-- DRC BICLayout.dale (we need a programming interface)
-- Plots
CDPlot Sleepy -k CHIPLayout
-- Plot BICLayout.dale and eyeball it
-- Use the shell to produce a bonding map; make sure that all bonding and wiring constraints are satisfied
-- Generate the Mebes files
source CDMEBESCMOSB31Jul87.load
← %CDMEBES.stripesPerClump ← 5;
← %CDMEBES.wDir ← "///mebes/"
← &design ← PW.OpenDesign["BICLayout"]
← CDProperties.PutDesignProp[&design, $CDMEBESMaskSetName, "BIC56789"]
-- 9 chars, alphanum
← CDMEBESMainImpl.StartMEBESMask[NEW[CDSequencer.CommandRec ← [design: &design]]]
-- generates a bunch of files of the form BIC56789.AAA
-- Smodel under /indigo/dragon7.0/BIC12Oct87.df and archive immediately
-- Visit your travel agent for good prices for Tahiti