Bus Interface Chip
BIC Data sheet
Richard Bruce, Louis Monier
Dragon-86-xx Written February 1987 Revised September, 1987
Copyright 1986 Xerox Corporation. All rights reserved.
Abstract: The Bus Interface Chip (BIC) is a component of the June87 machine. It connects the chips residing on an hybrid (cache, map cache, memory controller, IOBridge, display controller, ...) to the fast 2V bus.
The first design was by Alfred Permuy during the summer of 1986. Richard Bruce took over the logic design and Louis Monier the physical implementation. The first version was submitted in May 87 and tested in August 87. The second version was sent to fab in November 87 with minor changes to track new specs. This document applies to the second version.
Keywords: BIC, Bus Interface Chip, June87 computer
FileName: /Indigo/Dragon7.0/BIC/BICDoc.tioga, .interpress
XEROX  Xerox Corporation
   Palo Alto Research Center
   3333 Coyote Hill Road
   Palo Alto, California 94304

Dragon Project - For Internal Xerox Use Only
1. Overview
2. Pinout
3. Block Diagram
4. Signals definition
5. Timing
6. Application schematics
Appendix A. Appendix A Title
Appendix B. Appendix B Title
1. Data sheet
Pin configuration and icon
block diagram
1. Overview
The Bus Interface Chip (BIC) is a relatively small but critical component of the June87 machine. It provides the interface between the chips inside an hybrid (Cache, Display Controller, Memory Controller, IOBridge, Map Cache, ...) and the Dynabus (the fast terminated 2V bus).
Every hybrid (or board in the wire-wrapped prototype) holds up to four BICs. BICs are also present on the backplane.
BIC provides an electrical insulation between the fast 2V bus and the 5V hybrid bus. In addition the DBus control logic, and the clock amplification stages and skew control logic for a hybrid are located on the chip.
2. Functionnal and electrical requirements
2.1 Data transfer
The main function of BIC is to provide access of client circuits to the Dynabus.
Hybrid to board: BIC has 24 data channels enabled by the OR of four grant lines (Send), two Request lines and four signals which are ORed together. All these signals are latched and inverted before being put on the Dynabus. Typically, four clients can wire-OR a fraction of their Dynabus ouput signals on the data lines.
Board to hybrid: 24 data channels provide the Dynabus input data to client chips on the hybrid.
2.2 DBus amplification
BIC also provides 3 pairs of generic inverting buffers for various DBus signals. These are not strictly necessary, but are used to guarantee that the DBus will not be arbitrarily slow. The hybrid to board lines are typically used for amplifying DBusOut and are enabled by DOEn.
2.3 Clock generation and skew control
A pair of delay lines controlled from DBus-loadable 4-bit registers are used to set the skew between an early clock nEarly and the local or external clock LocCKOut and ExtCKOut. This mechanism is temporary and will be replaced by VCO-based logic.
2.4 Electrical requirements
On the Dynabus side, input signals vary in the 0 to +2V range and are received through a threshold-adjustable receiver (RecAdj). Clocks are also 2V signals, and have similar receivers controlled by CKRecAdj. The proper value for these voltages is to be determined experimentally; ultimately, they will be generated internally by an appropriate pile of analog logic.
Ouput signals are pulled-down only since the Dynabus has external pull-up resistors connected to +2V. A weak pull-up can also bring (ver-r-r-y slo-o-o-owly) these lines up. These pull-ups have no role in practice; they are mostly present for testing and simulation convenience.
On the hybrid side, all signals are CMOS-level (0 to +5V).
3. Signals definition
3.1 Power supplies
The BIC uses two sets of power supplies: Vdd (+5V) and Gnd (0V) for the logic and the hybrid pad drivers, and Gnd2V (0V) for the Dynabus drivers. The two Gnd are not connected on the chip to prevent spikes generated when driving the Dynabus to affect the logic.
Two external analog voltages, RecAdj and CKRecAdj, control the threshold of the Dynabus receivers and clock receivers, respectively.
3.2 Clocks
BIC receives seven clock-related signals used to perform several functions: run a reference clock through two DBus-controlled delay lines, provide clock to another chip on the hybrid (the client), compare its clock and the client's clock with a reference clock.
nEClock: the inverted early clock; runs through two delay lines.
LocCKOut: the output of one delay line; normally connected to ChipCKIn.
ExtCKOut: the output of the other delay line; provides clock to its client.
ChipCKIn: the high-power clock for BIC itself; amplified twice and distributed.
ChipCKOut: the result of amplifying ChipCKIn.
ExtCKIn: the clock sent back by the client, after amplification.
Clock: the reference clock, used to sample ExtCKIn and ChipCKOut.
3.3 DBus
DBusIn[0..7): the usual DBus plus HybridSel.
DBusOut: the output of the DBus scan path; tristate when unused.
DCS[0..3): DBus chip select, to address any of 3 other chips on the hybrid.
nSStop: the synchronous stop.
DOEn: enables the DBus drivers on the Dynabus side.
Name[0..3): a constant value hardwired through bonding.
3.4 Communication with the hybrid
BInH[0..24): generic data signals from the hybrid. Enabled by Send; latched.
RqIn[0..2): request signals from the hybrid; latched.
OrInH[0..4): ORed together; latched.
DInH[0..3): DBus signals from the hybrid.
BOutH[0..24): generic data signals to the hybrid (from nBInB); latched.
DOutH[0..24): DBus signals to the hybrid (from nDInB).
3.5 Communication with the arbiter
Send[0..4): the four wires are ORed, latched once, and enable the BInH inputs.
3.6 Communication with the Dynabus
nBInB[0..24): generic data signals from the Dynabus; latched.
nDInB[0..3): DBus signals from the Dynabus.
nBOutB[0..24): generic data signals to the Dynabus (from BInH).
nOrOutB: to Dynabus (from OrInH).
nRqOutB[0..2): request signals to the Dynabus (from RqIn).
nDOutB[0..3): DBus signals to the Dynabus (from DInH).Enabled by DOEn.
4. Access through the DBus
Most internal states of BIC are acessible through the DBus.
4.1 DBus address register
An 8-bit shift register, loaded when DAddress. The 3 high-order bits CID are compared to the Name of this particular BIC. If match and ~DAddress and HybridSel then the following two bits CS are decoded into four bits. The three low-order bits DCS are used to address others circuits on the hybrid. The high order bit is used to enable a decoding of the remaining 3 low-order bits in the address register (RS). This 3-to-8 deocoder is used to address the internal scan path of the BIC according to the table:
0: ReadChipID
1: AccessDP
2: ReadExtCK
3: ReadIntCK
4: WriteExtCK
5: WriteIntCK
6, 7: N/A
4.2 Chip ID
This 16-bit shift register is loaded when DAddress is asserted. It's the scan path number 0 by DBus requirement. The value is 5081H=0101,000010,000001 where 0101 is the mandatory pattern, 2 is the type (BIC) and 1 is the version.
4.3 Data path
Most flops in the data path are connected to form a 2*(24+2)=52-bit shift register, scan path number 1. The exception is the flop preceeded by a 4-input OR, used by SStop, Shared and Owner. DShiftCK is differentiated to produce a one cycle pulse used to shift the register. The order is, starting on lsb:
- the data: BOutH[23], nBOutB[23], BOutH[22], ... , nBOutB[0]
- Request: extra0, nRqOutB[1], extra1, nRqOutB[0]
Notice the existence of two extra flops which can be accessed only through shift or reset; they are present only for layout reason.
Since flops of BOutH (and the extras) are reset to 1 and flops of nBOutB and nRqOutB are reset to 0, the pattern after reset is (01)26.
4.4 Clock registers
The skew of the internal and external clocks can be controlled through two independent 4-bit shift registers, which can be read or written. The scan paths are 2 (read external), 3 (read internal), 4 (write external), 5 (write internal).
5. Title
All paragraphs in a Dragon document have the format body, except for paragraphs that continue after an equation or an in-line figure. These have the format block. All headings have the format head. Chapters should begin on an odd-numbered page, so a pageBreak node should be placed just prior to the chapter.
A node which defines the running head can be inserted nested under the chapter heading. It has the node property Mark with value centerRectoHeader. The TSetter understands this to be a header definition and diverts the text for later assembly during page layout. All paragraphs in a blue-and-white have the format body.
3.1 SubSection Title
3.2 SubSection Title
Appendix A. Pinout
The circuit is 14080m wide by 3173m tall; these dimensions are fixed in order to re-use the probe card and work on hybrid. The Dynabus (board) pads occupy the top, and the corresponding hybrid pads the bottom. Control and clock signals share the left and right sides.
This wierd aspect ratio is due to bonding and routing constraints on the hybrid. For that reason, in the wire-wrapped prototype, BIC can only fit into a large 300-pin PGA with a 17.75mm cavity.
Appendix B. Appendix B Title
Louis Monier September 6, 1987 2:50:09 pm PDT
Wrote most of the document from older pieces of informations.
Louis Monier November 12, 1987 1:33:05 pm PST
Removed the or4-flop from the scan path.