BICDataSheetDoc.tioga
The Bus Interface Chip
The Bus Interface Chip
XEROX PRIVATE DATA
XEROX PRIVATE DATA
XEROX PRIVATE DATA
The Bus Interface Chip
Louis Monier
CSL-88-xx March 1988 [Dragon-88-3]
© Copyright 1988 Xerox Corporation. All rights reserved.
Keywords: Bus Interface Chip, BIC, Data sheet, Dragon, DynaBus, DBus;
Maintained by: Louis Monier
XEROX   Xerox Corporation
    Palo Alto Research Center
    3333 Coyote Hill Road
    Palo Alto, California 94304

For Internal Xerox Use Only
Bus Interface Chip
1.0 Brief Description
The Bus Interface Chip (BIC) is a relatively small but critical component of the June87 machine. It provides the interface between the chips inside an hybrid (Cache, Display Controller, Memory Controller, IOBridge, Map Cache, ...) and the Dynabus (the fast terminated 2V bus).
Every hybrid (or board in the wire-wrapped prototype) holds up to four BICs. BICs are also present on the backplane.
BIC provides an electrical insulation between the fast 2V bus and the 5V hybrid bus. In addition the DBus control logic, and the clock amplification stages and skew control logic for a hybrid are located on the chip.
This data sheet corresponds to the third version of BIC (known as BIC3), generated during the Spring 1988.
2.0 Pin-Out
This is a schematic describing the pin-out of the circuit. Show the pins in the order that would be easiest for an intelligent, uninformed reader to understand. For circuits connecting to the DynaBus show all DynaBus connections on the left side and all other connections on the right. (Section 9.0 gives the actual physical layout of the pins.)
Figure 1: The Pin-Out of BIC.
3. Block Diagram of the Chip
This diagram includes the high-level functional blocks of the circuit.
4.0 Detailed Description of Each of the Functional Blocks
4.1 Data path
4.1.1 The main Data Ports
Hybrid to board: BIC has 24 data channels enabled by the OR of four grant lines (Send), two Request lines and four signals which are ORed together. All these signals are latched and inverted before being put on the Dynabus. Typically, four clients can wire-OR a fraction of their Dynabus ouput signals on the data lines.
Board to hybrid: 24 data channels provide the Dynabus input data to client chips on the hybrid.
4.1.2 The Device Request Ports
Each.
4.1.3 The Wired-or Ports
Each.
4.2 DBus
4.2.1 DBus address register
An 8-bit shift register, loaded when DAddress. The 3 high-order bits CID are compared to the Name of this particular BIC. If match and ~DAddress and HybridSel then the following two bits CS are decoded into four bits. The three low-order bits DCS are used to address others circuits on the hybrid. The high order bit is used to enable a decoding of the remaining 3 low-order bits in the address register (RS). This 3-to-8 deocoder is used to address the internal scan path of the BIC according to the table:
0: ReadChipID
1: AccessDP
2: ReadExtCK
3: ReadIntCK
4: WriteExtCK
5: WriteIntCK
6, 7: N/A
4.2.1 Chip ID
This 16-bit shift register is loaded when DAddress is asserted. It's the scan path number 0 by DBus requirement. The value is 5081H=0101,000010,000001 where 0101 is the mandatory pattern, 2 is the type (BIC) and 1 is the version.
4.2.1 Data path
Most flops in the data path are connected to form a 2*(24+2)=52-bit shift register, scan path number 1. The exception is the flop preceeded by a 4-input OR, used by SStop, Shared and Owner. DShiftCK is differentiated to produce a one cycle pulse used to shift the register. The order is, starting on lsb:
- the data: BOutH[23], nBOutB[23], BOutH[22], ... , nBOutB[0]
- Request: extra0, nRqOutB[1], extra1, nRqOutB[0]
Notice the existence of two extra flops which can be accessed only through shift or reset; they are present only for layout reason.
Since flops of BOutH (and the extras) are reset to 1 and flops of nBOutB and nRqOutB are reset to 0, the pattern after reset is (01)26.
4.2.2 Clock registers
The skew of the internal and external clocks can be controlled through two independent 4-bit shift registers, which can be read or written. The scan paths are 2 (read external), 3 (read internal), 4 (write external), 5 (write internal).
4.2.3 The DBus buffers
BIC also provides 3 pairs of generic inverting buffers for various DBus signals. These are not strictly necessary, but are used to guarantee that the DBus will not be arbitrarily slow. The hybrid to board lines are typically used for amplifying DBusOut and are enabled by DOEn.
4.3 Clocks
4.1.1 Skew control
A pair of delay lines controlled from DBus-loadable 4-bit registers are used to set the skew between an early clock nEarly and the local or external clock LocCKOut and ExtCKOut. This mechanism is temporary and will be replaced by VCO-based logic.
4.1.2 Amplification
Load.
5.0 Detailed Description of Each Pin
Following the order of pins given in Section 2.0, describe each of the pins. A couple of examples follow. Copy more table entries as needed.
Pin Name I/O Pin Description
Vdd I The positive power supply+5V; provided through 16 pins
Gnd I The common ground provided through 16 pins. Used by all circuitry except the final stage of low-voltage amplifiers.
Gnd2V I A special ground used only by the pull-down on the last stage of the 30 low-voltage amplifiers. It is available as a solid bar on top of the circuit, and offers 38 double-bonding sites.
RecAdj I RecAdj is an approximately 3V analog signal that sets the threshold on 2V external logic receivers.
CKRecAdj I CKRecAdj is similar to RecAdj, but used to adjust the threshold of the receiver for Clock and nEClock.
nEClock I The inverted early clock runs through a digital delay line and amplification stages to become the clock for BIC and a slave circuit.
Clock I The reference clock is carefully distributed throughout the machine to minimize skew. Its load inside BIC is kept to a minimum: it is only used to sample ExtCKIn and ChipCKOut.
LocCKOut O The output of one delay line; it should normally be connected externally to ChipCKIn.
ChipCKIn I The high-power clock for BIC itself; it runs through a tw0-stage amplifier and is distributed throughout the chip.
ChipCKOut O The result of amplifying ChipCKIn, made public for testing purposes.
ExtCKOut O The output of the other delay line; it provides the clock to a slave chip.
ExtCKIn I The clock sent back by the slave after amplification. It can be compared to Clock and used to adjust the delay line.
DBusIn[0..7) I 
DBusOut O The output of the selected DBus scan path. It is a tri-state wire if no scan path is selected.
DCS[0..3) O The DBus chip select is used to address any of 3 other chips on the hybrid. Typically it is the DSelect of one slave.
DOEn I DBus Output Enable. When asserted, the three generic DBus drivers on the Dynabus side are active, otherwise they are tristate (high).
nSStop I The synchronous stop, asserted by the arbiter. Should not be used.
Send[0..4) I The four grant wires sent by the Arbiter to the slave chips in the hybrid. The four wires are ORed, latched once, and used to enable the BInH inputs.
Name[0..3) I A three-bit constant fixed during bonding, Name distinguishes among the different BICs on the same hybrid.
BInH[0..24) I generic data signals from the hybrid. Enabled by Send; latched
nBOutB[0..24) O generic data signals to the Dynabus (from BInH)
RqIn[0..2) I request signals from the hybrid; latched
nRqOutB[0..2) O request signals to the Dynabus (from RqIn).
OrInH[0..4) I ORed together; latched
nOrOutB O to Dynabus (from OrInH)
DInH[0..3) I DBus signals from the hybrid
nDOutB[0..3) O The inverted outputs of the three generic DBus drivers to the Dynabus (from DInH). Enabled by DOEn.
nBInB[0..24) I generic data signals from the Dynabus; latched
BOutH[0..24) O generic data signals to the hybrid (from nBInB); latched
nDInB[0..3) I DBus signals from the Dynabus
DOutH[0..3) O DBus signals to the hybrid (from nDInB)
6.0 DC Characteristics
Pin Name Signal Type Voltage  Current
Group A 2V input L 0.65 .035 ma
Group B 2V open drain output L 0.2 92 ma
Group C 5V input L 1.0 0
  H 4.0 0 
Group D 5V output L 0.0 0
  H 5.0 0
Group E analog input 2-4.5 V  0.1 ma
DBusOut 5V Tri-state L 0.0 0
  H 5.0 0
Pin Type Pin Name
Group A nEClock
 Clock
 nBInB[0..24)
 nDInB[0..3) ???
Group B nBOutB[0..24) 
 nRqOutB[0..2) 
 nOrOutB
 nDOutB[0..3) ???
Group C ChipCKIn
 ExtCKIn
 DBusIn[0..7)
 nSStop
 DOEn
 Name[0..3)
 BInH[0..24)
 RqIn[0..2)
 OrInH[0..4)
 DInH[0..3)
 Send[0..4)
Group D LocCKOut
 ExtCKOut
 ChipCKOut
 DCS[0..3)
 BOutH[0..24)
 DOutH[0..3) 
Group E RecAdj
 CKRecAdj
7.0. AC Characteristics
A. Definitions
The timing characteristic of each port are described in this section. It is generally assumed that the charcteristics of all the wires connecting a chip to a particular component are the same, so that Dynabus signals, DBug Bus signals, Backpanel signals, (etc.) may be characterized as a group.
[Artwork node; type 'Artwork on' to command tool]
Figure 4: Input Signal Characteristics
Ts (setup time) = the mimimum time a signal must be stable before the rising edge of the clock.
Th (hold time) = the mimimum time a signal must be stable after the rising edge of the clock.
[Artwork node; type 'Artwork on' to command tool]
Figure 5: Output Signal Characteristics
Tcycle = the time interval between successive rising edges of the clock
Tpd (propagation delay) = the waiting time after the clock is high until an output becomes valid.
Tm (maintenance of old data) = the time after rising edge of next clock cycle that old data remains valid.
B. Values
Qualififed Pin Name Tmin Ttypical Tmax
Tcycle 20ns 25ns 27ns
Ts.Dynabus In (setup.Dynabus In)  3ns 
Th.Dynabus In (hold.Dynabus In)  1ns
Tpd.Dynabus Out (propagation delay.Dynabus Out)  5ns
Tm.Dynabus Out (maintain.Dynabus Out)  2ns
   
   
8.0 Application Schematics of the Circuit
This schematic shows the top-level icon of the circuit being described and its connections to other top-level components in the system.
9.0 Physical Pin-Out For Each Package
The die is 14080m wide by 3173m tall; these dimensions are fixed in order to re-use the probe card and work on hybrid. The Dynabus (board) pads occupy the top, and the corresponding hybrid pads the bottom. Control and clock signals share the left and right sides.
This wierd aspect ratio is due to bonding and routing constraints on the hybrid. For that reason, in the wire-wrapped prototype, BIC can only fit into a large 300-pin PGA with a 17.75mm cavity.
No Name  No Name No Name No Name
4 nGrant.0 37 nOwnerOut 73 TIOvdd 110 ArbReqOut.0
5 nRequestOut.0.0 38 nSharedOut.0 74 TIOgnd 111 OtherArbIn.0.0
       
       
       
Here is an sample diagram indicating the range of pins that are located on each side of the PGA:
[Artwork node; type 'Artwork on' to command tool]