<> <> <> <> <> Statistics on -- you always want to know how long it took ColorDisplayModeOff -- saves a lot of cycles Install DAUser SC PadFrames <<-- and anything else you might need such as FSA, DP, Alps, ..., or any of your private code>> _ CedarProcess.SetPriority[background] _ &design _ PW.OpenDesign["Arbiter25.dale"] -- read the CD design _ &cx _ Sisyph.Create[&design, NIL] -- this creates a context for Sysiph <<>> <<-- Generate celltype: the top-level schematic is read and extracted>> _ &ct _ Sisyph.ES["ArbInFrame.sch", &cx] _ PWCore.SetLayout[&ct, $SCRemote] -- this extracts the top-level schematic <<>> <<-- Apply Static>> <> <<_ Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]]>> <<-- errors can be found found in the terminal>> <<-- Apply MintCheck>> <> <<_ &circuit _ Mint.CreateCircuit[&ct]>> <<_ MintCmds.PrepareCircuit[&circuit, FALSE];>> <<_ Mint.CheckLibrary[&circuit]>> <<-- errors can be found found in the terminal>> <<-- make a note of this number of transistors, and write home about it>> <<-- you also get an estimation of the total capacitance which you can use to derive an upper bound on the average power consumption.>> <<>> <<-- Generate Layout>> _ &ob _ PWCore.Layout[&ct] <<-- creates the CD object and attaches it to the cellType>> _ PWCore.Store[&ct, TRUE] <<-- saves the decorated Core under BIC.core, the layout under BICLayout.dale, and a view of the public pins under BICShell.dale>> <<-- the decorated Core will be read back for future work>> <<-- the layout will be DRCed, plotted, and turned into a Mebes file>> <<-- the shell will be needed to check the pad position and make the probing and bonding maps>> _ PW.Draw[&ob] <<>> <<>> <<-- Compare layout and schematics>> <> <<_ CoreProperties.PutCellTypeProp[on: &ct, prop: StructuralComparisonDataStructure.transistorTolerancesKey, value: NEW [StructuralComparisonDataStructure.TransistorTolerancesPrivate _[[0.5, 2.0], [0.5, 2.0]]]]>> <<-- no kidding; min and max acceptable ratio on length and width of transistors>> <<_ PWCoreLichen.Compare[&ct]>> <<-- compares the cellType with the extracted layout>> <<>> <<-- Check the connectivity>> <> <> <<-- signals all disconnected internals; returns a list of disconnected publics>>