LayoutArbInFrame.cm
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Created by: Louis Monier August 20, 1987 6:05:52 pm PDT
Last Edited by: Louis Monier September 19, 1987 9:20:32 pm PDT
Last Edited by: McCreight September 19, 1987 9:20:34 pm PDT
Statistics on
-- you always want to know how long it took
ColorDisplayModeOff
-- saves a lot of cycles
Install DAUser
SC PadFrames
-- and anything else you might need such as FSA, DP, Alps, ..., or any of your private code
← CedarProcess.SetPriority[background]
← &design ←
PW.OpenDesign["Arbiter25.dale"]
-- read the CD design
← &cx ← Sisyph.Create[&design,
NIL]
-- this creates a context for Sysiph
-- Generate celltype: the top-level schematic is read and extracted
← &ct ← Sisyph.ES["ArbInFrame.sch", &cx]
← PWCore.SetLayout[&ct, $SCRemote]
-- this extracts the top-level schematic
-- Apply Static
Install Static
← Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]]
-- errors can be found found in the terminal
-- Apply MintCheck
Install Mint
← &circuit ← Mint.CreateCircuit[&ct]
← MintCmds.PrepareCircuit[&circuit, FALSE];
← Mint.CheckLibrary[&circuit]
-- errors can be found found in the terminal
-- make a note of this number of transistors, and write home about it
-- you also get an estimation of the total capacitance which you can use to derive an upper bound on the average power consumption.
-- Generate Layout
← &ob ← PWCore.Layout[&ct]
-- creates the CD object and attaches it to the cellType
← PWCore.Store[&ct,
TRUE]
-- saves the decorated Core under BIC.core, the layout under BICLayout.dale, and a view of the public pins under BICShell.dale
-- the decorated Core will be read back for future work
-- the layout will be DRCed, plotted, and turned into a Mebes file
-- the shell will be needed to check the pad position and make the probing and bonding maps
← PW.Draw[&ob]
-- Compare layout and schematics
Install PWCoreLichen
← CoreProperties.PutCellTypeProp[on: &ct, prop: StructuralComparisonDataStructure.transistorTolerancesKey, value: NEW [StructuralComparisonDataStructure.TransistorTolerancesPrivate ←[[0.5, 2.0], [0.5, 2.0]]]]
-- no kidding; min and max acceptable ratio on length and width of transistors
← PWCoreLichen.Compare[&ct]
-- compares the cellType with the extracted layout
-- Check the connectivity
Install ConnectivityChecker
CheckConnectivity BICLayout.dale
-- signals all disconnected internals; returns a list of disconnected publics