ArbiterChipTest.mesa
Don Curry March 9, 1988 7:36:27 pm PST
DIRECTORY
CommandTool, Core, CoreIO, CoreOps, IcPack, ICTest, IO, Ports, PodToTesterConfigPin, ProbePinToDUTConfigPin, Rope, RosemaryUser, RosemaryVector, SymTab, TestCable;
ArbiterChipTest: CEDAR PROGRAM
IMPORTS CommandTool, CoreIO, CoreOps, IcPack, ICTest, IO, PodToTesterConfigPin, ProbePinToDUTConfigPin, Rope, RosemaryVector, SymTab, TestCable
= BEGIN
Arbiter Specific
deviceNm:   IO.ROPE = "Arbiter";
packageNm:   IO.ROPE = Rope.Cat[deviceNm, "IcPack"];
cacheNm:    IO.ROPE = Rope.Cat[deviceNm, "IcPackCache"];
testName:    IO.ROPE = Rope.Cat[deviceNm, " Chip Test"];
vecTestProcName: IO.ROPE = Rope.Cat[deviceNm, "Test"];
packageCell:   Core.CellType ← IcPack.GetDesignCellType[packageNm];
referenceCell:  Core.CellType ←
CoreOps.SetCellTypeName[ CoreIO.RestoreCellType[cacheNm], deviceNm];
units:     NAT ← 10;   -- ns
lastPeriod:   NAT ← 40*units; -- ns
initCkDel:   NAT ← 16*units;
initWidth:   NAT ← 20*units;
initAcquire:   NAT ← 32*units;
ReverseBdPodGrps:  PROC[list: BdPodGrps] RETURNS[new: BdPodGrps] =
{FOR list ← list, list.rest WHILE list#NIL DO new ← CONS[list.first, new] ENDLOOP};
InitChipTest:  PROC = {
assignments  ← NIL;
groups   ← NIL;
nxtGrp   ← 0;
bdPodGrpsRev ← ReverseBdPodGrps[LIST[
[[0, rec, L, AB], "DevIn", "DevIn" ], [[0, dr, R, AB], "DevOut", "DevOut" ],
[[1, rec, L, CD], "ArbIn", "ArbIn" ], [[1, dr, R, CD], "ArbOut"     ],
[[2, rec, L, EF], "ArbIn", "OrIn" ], [[2, dr, R, EF],        ],
[[3, rec, L, GH], "OrIn", "OrIn" ], [[3, dr, R, GH], "OrOut"     ],
[[4, rec, L, IJ], "DBIn", "OthIn" ], [[4, dr, R, IJ], "DBOutT", "OthOut" ],
[[5, rec, L, KL], "ClockIn"    ], [[5, dr, R, KL], "ClockOut"    ] ] ];
Grp[nm:"DevIn",  dir: force, for: NRZ,         sigs: LIST[
"nRequestOut"] ]; -- 16
Grp[nm:"ArbIn",   dir: force, for: NRZ,         sigs: LIST[
"OtherArbInT" ] ]; -- 21
Grp[nm:"OrIn",   dir: force, for: NRZ,         sigs: LIST[
"nSharedOut",  -- 8
"nSStopOut",  -- 8
"nOwnerOut",
"nBOwnerIn",
"nStopAct"] ];
Grp[nm:"DBIn",   dir: force, for: NRZ,         sigs: LIST[
"DBus[0]",
"DBus[1]",
"DBus[2]",
"DBus[3]",
"DBus[4]",
"DBus[5]" ] ];
Grp[nm:"OthIn",   dir: force, for: NRZ,         sigs: LIST[
"SlotNo",   -- 4
"BdVersion"] ]; -- 2
Grp[nm:"ClockIn",  dir: force, for: RZ, del: initCkDel, wid: initWidth, sigs: LIST[
"Clock"] ];
Grp[nm:"DevOut",  dir: acquire, sam: initAcquire,      sigs: LIST[
"nGrant",   -- 8
"nHiPGrant",
"nLongGrant",
"nStartGrant"] ];
Grp[nm:"ArbOut",  dir: acquire, sam: initAcquire,      sigs: LIST[
"ArbReqOut",  -- 3
"nBusyOut"] ];
Grp[nm:"OrOut",  dir: acquire, sam: initAcquire,      sigs: LIST[
"nBOwnerOut",
"nBSharedOut",
"nBSStopOut",
"nOwnerIn",
"nSharedIn",
"nSStopIn"] ];
Grp[nm:"DBOutT",  dir: acquire, sam: initAcquire,      sigs: LIST[
"DBus[6]"] ];
Grp[nm:"OthOut",  dir: acquire, sam: initAcquire,      sigs: LIST[
"nDHybridSel", -- 5
"DBdSel"] ];
Grp[nm:"ClockOut",  dir: acquire, sam: initAcquire,      sigs: LIST[
"CKOut"] ];
Unassigned ← LIST[
"RecAdj",
"TInv",  -- 2
"TIOBus", -- 6
"TRec2v", -- 3
"Vdd",
"Gnd",
"Gnd2VTop",
"Gnd2VTop"];
ConfiguratorWires.FillInHeaderPins[deviceName, assignments, ProbePinToDUTConfigPin.Map]
ConfiguratorWires.MakeWireListForMike[deviceName, assignments]
OPen deviceName.assignments
OPen deviceName.wires
TestCable.Init[groups, assignments, "Clock"];
ICTest.MakeStandardViewer[
testName:  testName,
cellType:  referenceCell,
clockAName: "Clock",
clockBName: "PhB",
groups:  groups,
assignments: assignments,
period:  lastPeriod ]};
Types
Board:    TYPE = ICTest.Board;
Dir:    TYPE = ICTest.Directionality[force..acquire];
LdSide:   TYPE = ICTest.LoadBoardSide;
PodPair:   TYPE = ICTest.PodPair;
PodByte:   TYPE = ICTest.PodTiming; -- A, B
Channel:   TYPE = ICTest.Channel;
RecDr:   TYPE = {rec, dr};
BdPodGrps:  TYPE = LIST OF BdPodGrp ← NIL;
BdPodGrp:  TYPE = RECORD[bdPod: BdPod, grpA: IO.ROPE ← NIL, grpB: IO.ROPE ← NIL];
BdPodBytes:  TYPE = LIST OF BdPodByte ← NIL;
BdPodByte:  TYPE = RECORD[bdPod: BdPod, podByte: PodByte];
BdPod:   TYPE = RECORD[board: Board, recDr: RecDr, ldSide: LdSide, podPair: PodPair];
SigPkgPin:  TYPE = RECORD[sig: IO.ROPE, pin: INT];
SigPkgPins:  TYPE = LIST OF SigPkgPin;
Generic
initialWDir:  IO.ROPE ← CommandTool.CurrentWorkingDirectory[];
assignments:  ICTest.Assignments  ← NIL;
groups:   ICTest.Groups   ← NIL;
bdPodGrpsRev: BdPodGrps ← NIL;
sigPkgPinTab: SymTab.Ref;
nxtGrp:   NAT ← 0;
SigPkgPinList: PROC[signal: IO.ROPE] RETURNS[result: SigPkgPins] = {
EachAtomic: PROC[wire: Core.Wire] ~ {
name: IO.ROPE
← IcPack.AtomicName[CoreOps.GetFullWireName[referenceCell.public, wire]];
pin: REF INT ← NARROW[SymTab.Fetch[sigPkgPinTab, name].val];
IF pin=NIL THEN ERROR;
list ← CONS[[name, pin^], list]};
list:  SigPkgPins ← NIL;
sigWire: Core.Wire ← CoreOps.FindWire[referenceCell.public, signal];
IF sigWire=NIL THEN ERROR;
IF sigPkgPinTab=NIL THEN
sigPkgPinTab ← IcPack.GetPkgNameTab[ packageCell ];
CoreOps.VisitRootAtomics[sigWire, EachAtomic];
FOR list ← list, list.rest WHILE list#NIL DO result ← CONS[list.first, result] ENDLOOP};
Grp:    PROC[
nm: IO.ROPE,
dir: ICTest.Directionality,
for: ICTest.FormatType ← DNRZ,
del: ICTest.Delay   ← 0,
wid: ICTest.Width   ← initWidth,
sam: ICTest.Sample  ← 0,
sigs: LIST OF IO.ROPE ] = {
group: ICTest.Group ← [
number: nxtGrp,  name: nm, directionality: dir,
format: for,   delay: del, sample: sam,   width: wid];
channel:  Channel ← 0;
bdPodBytes: BdPodBytes ← NIL;
groups  ← CONS[group, groups];
nxtGrp  ← nxtGrp + 1;
FOR bpg: BdPodGrps ← bdPodGrpsRev, bpg.rest WHILE bpg#NIL DO
IF bpg.first.grpB.Equal[nm] THEN
bdPodBytes ← CONS[[bpg.first.bdPod, B], bdPodBytes];
IF bpg.first.grpA.Equal[nm] THEN
bdPodBytes ← CONS[[bpg.first.bdPod, A], bdPodBytes] ENDLOOP;
FOR sigs ← sigs, sigs.rest WHILE sigs#NIL DO
FOR list: SigPkgPins ← SigPkgPinList[sigs.first], list.rest WHILE list#NIL DO
assign: ICTest.Assignment ← [
name:    list.first.sig,
group:   groups.first.number,
board:    bdPodBytes.first.bdPod.board,
loadBoardSide: bdPodBytes.first.bdPod.ldSide,
podPair:   bdPodBytes.first.bdPod.podPair,
pod:    bdPodBytes.first.podByte,
channel:   channel,
testerHeader:  0,
dUTHeader:  ProbePinToDUTConfigPin.Map[list.first.pin],
probeCardPin: list.first.pin];
assign.testerHeader ← PodToTesterConfigPin.Map[
s: assign.loadBoardSide,
p: assign.podPair,
c: assign.channel];
assignments ← CONS[assign, assignments];
channel ← (channel +1) MOD 8;
IF channel=0 THEN bdPodBytes ← bdPodBytes.rest ENDLOOP ENDLOOP};
Signal: SIGNAL = CODE;
ChangeTime: ICTest.PeriodChangeProc = {
UnitGrid: PROC[val: INT] RETURNS[INT] = {RETURN[((val + units/2)/units)*units]};
period ← UnitGrid[period];
IF period NOT IN [50..40000) THEN {Signal; RETURN};
IF period # lastPeriod THEN FOR gr: ICTest.Groups ← groups, gr.rest WHILE gr#NIL DO
gr.first.delay  ←    (gr.first.delay * period)/lastPeriod;
gr.first.width  ← UnitGrid[ (gr.first.width * period)/lastPeriod];
gr.first.sample ←    (gr.first.sample * period)/lastPeriod;
IF gr.first.delay NOT IN [0..31000) THEN ERROR; --valid in 1nS increments
IF gr.first.width NOT IN [20..31000) THEN ERROR; --valid in 10nS increments
IF gr.first.sample NOT IN [0..31000) THEN ERROR; --valid in 1nS increments
ENDLOOP;
lastPeriod ← period;
RETURN[groups]};
VectorTest:  PROC [file: IO.ROPE, p: Ports.Port, Eval: RosemaryUser.TestEvalProc] = {
fullfile: IO.ROPE ← initialWDir.Cat[file, ".vectors"];
vectorFile: RosemaryVector.VectorFile ← RosemaryVector.OpenVectorFile[fullfile, p];
DO
ENABLE IO.EndOfStream => EXIT;
RosemaryVector.ReadVector[vectorFile]; Eval[]; ENDLOOP};
VecTestProc:  ICTest.TestProc = {VectorTest[vecTestProcName, p, Eval]};
Initialization
InitChipTest[];
ICTest.RegisterTestProc[testName,    vecTestProcName, VecTestProc];
ICTest.RegisterTestProc[testName,    "TestCable",   TestCable.TestCable];
ICTest.RegisterPeriodChangeProc[testName,       ChangeTime];
END.