Arbiter.mesa
Copyright c 1987 by Xerox Corporation. All rights reserved.
McCreight May 13, 1987 3:32:57 pm PDT
Last Edited by: McCreight September 17, 1987 3:19:19 pm PDT
DIRECTORY BitOps, CoreCreate, Ports, RosemaryUser;
Arbiter: CEDAR DEFINITIONS
= BEGIN
maxArbiters: NAT = 8;
Arbiters: TYPE = [0..maxArbiters);
OtherArbiters: TYPE = [0..maxArbiters-1);
There are up to eight arbiters in a Dragon system.
maxDevices: NAT = 8;
Devices: TYPE = [0..maxDevices);
And each arbiter connects to up to eight requesting devices.
Priority: TYPE = [0..8) ← 7;
0 is best-priority
HoldPriority: Priority = 2;
If 2 is the best-priority request, then no grant is made.
NoRequestPriority: Priority = 7;
PacketLength: TYPE = MACHINE DEPENDENT {short2(0), long5(1)} ← short2;
DevPortParams: TYPE = RECORD [
priority: Priority ← 7,
length: PacketLength ← short2
];
DevReqType: TYPE = MACHINE DEPENDENT {L(0), H(1)} ← L;
DevReqCode: TYPE = MACHINE DEPENDENT {release(0), seize(1), reqL(2), reqH(3)} ← release;
ReqCount: TYPE = [0..6] ← 0;
ArbParams: TYPE = REF ArbParamsRec ← NIL;
ArbParamsRec: TYPE = RECORD [
whoAmI: Arbiters ← 0,
ports: ARRAY Devices OF ARRAY DevReqType OF DevPortParams
];
RequesterStateRec: TYPE = RECORD [
probs: REF ProbabilitiesRec ← NIL,
state: REFNIL
];
ProbabilitiesRec: TYPE = RECORD [ -- one in x
request: ARRAY DevReqType OF INTALL[100],
hold: INT ← 1000
];
DSerialOut: NAT = 0; -- DBus wire indexes
DSerialIn: NAT = 1;
nDReset: NAT = 2;
nDFreeze: NAT = 3;
DExecute: NAT = 4;
DAddress: NAT = 5;
DShiftCK: NAT = 6;
Owner, Shared, and SStop have are named as viewed by the arbiter's client (e.g., cache, memory controller, or what-have-you). Thus OwnerOut is sent from a cache to its arbiter. The "B" versions of those signals are as viewed from the arbiter, since they are strictly arbiter-to-arbiter negotiation. The notion is that one of these signals goes "out" until it reaches the backpanel, at which point is turns around and goes "in" until it reaches its destination.
nOwnerOut: NAT = 0; -- OSSIn wire indexes
nBOwnerIn: NAT = 1;
nSharedOut: NAT = 2;
nBSharedIn: NAT = 3;
nSStopOut: NAT = 4;
nBSStopIn: NAT = 5;
nBOwnerOut: NAT = 0; -- OSSOut wire indexes
nOwnerIn: NAT = 1;
nBSharedOut: NAT = 2;
nSharedIn: NAT = 3;
nBSStopOut: NAT = 4;
nSStopIn: NAT = 5;
PriorityRecLen: NAT = 9;
PriorityRec: TYPE = MACHINE DEPENDENT RECORD [
unused (0: 0..6): [0..128) ← 0,
hiP (0: 7..9): [0..8) ← 0,
hiLong (0: 10..10): BOOLFALSE,
loP (0: 11..13): [0..8) ← 0,
loLong (0: 14..14): BOOLFALSE,
nFIFOEna (0: 15..15): BOOLFALSE
];
DBusInitList: TYPE = LIST OF REF ANYNIL;
DBusInitItem: TYPE = RECORD [
addr: BitOps.BitWord ← 0,
offset: NAT ← 0,
containerWidth: NAT ← BitOps.bitsPerDWord,
container: BitOps.BitDWord
];
ArbInFrameCT: PROC RETURNS [ ct: CoreCreate.CellType ];
ArbExceptDBusCodeCT: PROC RETURNS [ ct: CoreCreate.CellType ];
ArbDBusCodeCT: PROC RETURNS [ ct: CoreCreate.CellType ];
SchematicCT: PROC [ cellName, designName: CoreCreate.ROPE ] RETURNS [ ct: CoreCreate.CellType ];
ResetSchematicCT: PROC [ cellName: CoreCreate.ROPE ];
SimplestArbCT: PROC RETURNS [ ct: CoreCreate.CellType ];
Returns a single arbiter with two random request ports and the rest free
This will be used by other folks trying to simulate their stuff.
SimplestArbInit: PROC [cellType: CoreCreate.CellType, p: Ports.Port, Eval: PROC [memory: BOOLTRUE], dBusInit: DBusInitList ← NIL ];
CreateSanity: PROC RETURNS [ ct: CoreCreate.CellType ];
sanity check for not more than one grant, etc.
ArbRandReq: PROC RETURNS [ ct: CoreCreate.CellType ];
END.