<> <> <> <> << >> <> << >> <<>> <> <> <> <> << >> <> << >> <<>> <> <> <> <> <> << >> <> << >> <<>> <<-- Start everything and read in the source design>> Statistics on <<-- you always want to know how long it took>> ColorDisplayModeOff <<-- saves a lot of cycles>> Install DAUser <<-- SpiceOps>> <<-- and anything else you might need such as FSA, DP, Alps, ..., or any of your private code>> _ CedarProcess.SetPriority[background] cdread Arbiter25 <<-- read the CD design>> _ &design _ CDViewer.FindDesign["Arbiter25"] _ &cx _ Sisyph.Create[&design, NIL] <<-- this creates a context for Sysiph>> <<-- Generate SC block, whenever it changes>> <> <<_ &ctf _ Sisyph.ES["ArbInFrame.sch", &cx]>> <<_ CoreIO.ReportSaveCellType[&ctf, "ArbSchInFrame.core"]>> <<_ CoreOps.SetCellTypeName[&ctf, "ArbSchInFrame"]>> <<_ PWCore.SetLayout[&ctf, $SCRemote]>> <> <<-- or TWPalain or TWTregonsee>> <<_ &obf _ PWCore.Layout[&ctf]>> <<_ PWCore.Store[&ctf, TRUE] >> <<_ PW.Draw[&obf]>> <<-- Compare layout and schematics>> <> <<_ PWCoreLichen.Compare[&ctf]>> <<-- compares the cellType with the extracted layout>> <<>> <<>> -- Generate whole chip, assuming SC block has been cached on file _ &ct _ Sisyph.ES["Arbiter.sch", &cx] -- this extracts the top-level schematic -- _ CoreIO.ReportSaveCellType[&ct, "ArbSch.core"] <<-- Apply Static>> <> <<_ Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]]>> <<-- errors can be found found in the terminal>> <<>> <<-- Apply MintCheck>> <> <<_ &circuit _ Mint.CreateCircuit[&ct]>> <<_ MintCmds.PrepareCircuit[&circuit, FALSE];>> <<_ Mint.CheckLibrary[&circuit]>> <<-- errors can be found found in the terminal>> <<-- make a note of this number of transistors, and write home about it>> <<-- you also get an estimation of the total capacitance which you can use to derive an upper bound on the average power consumption.>> <<>> <<-- Simulate as completely as possible, at transistor level (assuming testproc)>> <> <<>> -- Generate Layout _ &ob _ PWCore.Layout[&ct] -- creates the CD object and attaches it to the cellType _ PWCore.Store[&ct, TRUE] -- saves the decorated Core under Arbiter.core, the layout under ArbiterLayout.dale, and a view of the public pins under ArbiterShell.dale -- the decorated Core will be read back for future work -- the layout will be DRCed, plotted, and turned into a Mebes file -- the shell will be needed to check the pad position and make the probing and bonding maps <<>> <<-- If your design is too large and must be done in several VMs, the trick is to produce decorated Core files from schematic for large blocks, and have the corresponding icons read the Core file instead of extracting the schematic. The receipe for making the decorated Core files is described above. The icon should be created by >> <> <<-- If the construction fits in one VM, it is better to remove intermediate checkpoints for final constructions.>> <<>> <<_ PW.Draw[&ob]>> <<>> <<-- Check the connectivity>> <> <> <<-- signals all disconnected internals; returns a list of disconnected publics>> <<>> <<-- DRC ArbiterLayout.dale (we need a programming interface)>> <<>> <<-- Plots>> <> <<-- Plot ArbLayout.dale and eyeball it>> <<>> <<-- Use the shell to produce a bonding map; make sure that all bonding and wiring constraints are satisfied>> <<>> <<-- Generate the Mebes files>> <> <<_ %CDMEBES.stripesPerClump _ 5;>> <<_ %CDMEBES.wDir _ "///mebes/">> <<_ &layDesign _ PW.OpenDesign["ArbiterLayout"]>> <<_ CDProperties.PutDesignProp[&layDesign, $CDMEBESMaskSetName, "ARBNOV87A"]>> <<-- 9 chars, alphanum>> <<_ CDMEBESMainImpl.StartMEBESMask[NEW[CDSequencer.CommandRec _ [design: &layDesign]]]>> <<-- generates a bunch of files of the form ///mebes/ARBNOV87A/ARBNOV87A.dd>> <<>> <<-- Smodel under /indigo/dragon7.0/Arbiter12Oct87.df and archive immediately>> <<>> <<-- Visit your travel agent for good prices for Tahiti>>