Arbiter:
CEDAR
DEFINITIONS
= BEGIN
ArbNov87A:
BOOL;
-- 19 Jan 88
implement the first fabricated version, or the current version.
maxArbiters: NAT = 8;
Arbiters: TYPE = [0..maxArbiters);
OtherArbiters:
TYPE = [0..maxArbiters-1);
There are up to eight arbiters in a Dragon system.
maxDevices: NAT = 8;
Devices:
TYPE = [0..maxDevices);
And each arbiter connects to up to eight requesting devices.
Priority:
TYPE = [0..8) ← 7;
0 is best-priority
HoldPriority: Priority = 2;
If 2 is the best-priority request, then no grant is made.
NoRequestPriority: Priority = 7;
PacketLength: TYPE = MACHINE DEPENDENT {short2(0), long5(1)} ← short2;
DevPortParams:
TYPE =
RECORD [
priority: Priority ← 7,
length: PacketLength ← short2
];
DevReqType: TYPE = MACHINE DEPENDENT {L(0), H(1)} ← L;
DevReqCode: TYPE = MACHINE DEPENDENT {release(0), seize(1), reqL(2), reqH(3)} ← release;
ReqCount: TYPE = [0..6] ← 0;
ArbParams: TYPE = REF ArbParamsRec ← NIL;
ArbParamsRec:
TYPE =
RECORD [
whoAmI: Arbiters ← 0,
ports: ARRAY Devices OF ARRAY DevReqType OF DevPortParams
];
RequesterStateRec:
TYPE =
RECORD [
probs: REF ← NIL,
state: REF ← NIL
];
never: INT = 10000000;
ProbabilitiesRec:
TYPE =
RECORD [
-- one in x
request: ARRAY DevReqType OF INT ← ALL[100],
hold: INT ← 1000,
stop: INT ← 1000,
owner: INT ← never,
shared: INT ← never
];
DSerialOut: NAT = 0; -- DBus wire indexes
DSerialIn: NAT = 1;
nDReset: NAT = 2;
nDFreeze: NAT = 3;
DExecute: NAT = 4;
DAddress: NAT = 5;
DShiftCK: NAT = 6;
Owner, Shared, and SStop have are named as viewed by the arbiter's client (e.g., cache, memory controller, or what-have-you). Thus OwnerOut is sent from a cache to its arbiter. The "B" versions of those signals are as viewed from the arbiter, since they are strictly arbiter-to-arbiter negotiation. The notion is that one of these signals goes "out" until it reaches the backpanel, at which point is turns around and goes "in" until it reaches its destination.
nOwnerOut: NAT = 0; -- OSSIn wire indexes
nBOwnerIn: NAT = 1;
nSharedOut: NAT = 2;
nBSharedIn: NAT = 3;
nSStopOut: NAT = 4;
nBSStopIn: NAT = 5;
nBOwnerOut: NAT = 0; -- OSSOut wire indexes
nOwnerIn: NAT = 1;
nBSharedOut: NAT = 2;
nSharedIn: NAT = 3;
nBSStopOut: NAT = 4;
nSStopIn: NAT = 5;
PriorityRecLen: NAT = 9;
PriorityRec:
TYPE =
MACHINE
DEPENDENT
RECORD [
unused (0: 0..6): [0..128) ← 0,
hiP (0: 7..9): [0..8) ← 0,
hiLong (0: 10..10): BOOL ← FALSE,
loP (0: 11..13): [0..8) ← 0,
loLong (0: 14..14): BOOL ← FALSE,
nFIFOEna (0: 15..15): BOOL ← FALSE
];
DefaultPriority: CARDINAL = LOOPHOLE[PriorityRec[hiP: 1, hiLong: TRUE, loP: 4, loLong: FALSE, nFIFOEna: TRUE]];
PRE: TYPE = INT ← DefaultPriority;
PRA:
TYPE =
ARRAY Devices
OF
PRE;
DBusInitList: TYPE = LIST OF REF ANY ← NIL;
DBusInitItem:
TYPE =
RECORD [
addr: BitOps.BitWord ← 0,
bits: Ports.BoolSequence
];
ArbInFrameCT: PROC [arbNo: INT ← 0, pra: PRA ← ALL[DefaultPriority]] RETURNS [ ct: CoreCreate.CellType ];
ArbExceptDBusCodeCT: PROC RETURNS [ ct: CoreCreate.CellType ];
ArbDBusCodeCT: PROC [arbNo: INT ← 0, pra: PRA ← ALL[DefaultPriority]] RETURNS [ ct: CoreCreate.CellType ];
SchematicCT:
PROC [ cellName, designName: CoreCreate.
ROPE ]
RETURNS [ ct: CoreCreate.CellType ];
ResetSchematicCT: PROC [ cellName: CoreCreate.ROPE ];
CreateSanity:
PROC
RETURNS [ ct: CoreCreate.CellType ];
sanity check for not more than one grant, etc.
CreateWireAnd:
PROC
RETURNS [ ct: CoreCreate.CellType ];
wire-AND gate, mostly for simulation.
ArbRandReq: PROC [ pre: PRE ← DefaultPriority, prob: REF ← NIL ] RETURNS [ ct: CoreCreate.CellType ];
GetSystemTests: PROC RETURNS [listOfTests: LIST OF CoreCreate.ROPE];
END.