-- Cache.df -- Last Edited by: Barth, July 31, 1984 12:20:17 pm PDT -- Last Edited by: Curry, February 1, 1985 3:03:46 pm PST -- Last Edited by: McCreight, July 29, 1985 6:02:46 pm PDT Exports [Indigo]Top> Cache.df 23-Sep-85 15:42:02 PDT Exports [Indigo]NewCache>Rosemary> Cache.load!4 29-Jul-85 16:24:45 PDT CacheSimpleSimulation.load!3 29-Jul-85 18:17:34 PDT Cache.expand!2 12-Jul-84 14:37:48 PDT Default.DragonVM!1 14-Mar-84 12:19:14 PST +CacheOps.bcd!17 17-Sep-85 12:37:51 PDT +CacheOpsImpl.bcd!18 17-Sep-85 12:38:02 PDT +Cache.bcd!25 23-Sep-85 15:34:17 PDT +CacheImpl.bcd!11 23-Sep-85 15:34:27 PDT Cache.roseSymbols!19 23-Sep-85 15:29:48 PDT Cache.Cache.rosePorts!19 23-Sep-85 15:29:39 PDT Cache.roseLoad!19 23-Sep-85 15:29:49 PDT Cache.partsAssertions!8 23-Sep-85 15:29:36 PDT +CacheEntries.bcd!10 23-Aug-84 10:59:10 PDT CacheEntries.roseSymbols!6 01-Feb-85 09:49:26 PST CacheEntries.CacheEntries.rosePorts!6 01-Feb-85 09:49:13 PST CacheEntries.roseLoad!6 01-Feb-85 09:49:26 PST +CacheEntry.bcd!12 01-Feb-85 09:27:46 PST CacheEntry.roseSymbols!5 01-Feb-85 09:27:34 PST CacheEntry.CacheEntry.rosePorts!5 01-Feb-85 09:27:19 PST CacheEntry.roseLoad!5 01-Feb-85 09:27:34 PST +CacheMInterface.bcd!12 01-Feb-85 09:20:25 PST CacheMInterface.roseSymbols!6 01-Feb-85 09:20:14 PST CacheMInterface.MInterface.rosePorts!6 01-Feb-85 09:19:51 PST CacheMInterface.roseLoad!6 01-Feb-85 09:20:15 PST +CacheMInterfaceMCAMDriver.bcd!11 01-Feb-85 08:13:10 PST CacheMInterfaceMCAMDriver.roseSymbols!2 29-Jan-85 22:15:26 PST CacheMInterfaceMCAMDriver.MCAMDriver.rosePorts!2 29-Jan-85 22:15:21 PST CacheMInterfaceMCAMDriver.roseLoad!2 29-Jan-85 22:15:26 PST +CacheMInterfaceMRAMDriver.bcd!12 01-Feb-85 08:12:31 PST CacheMInterfaceMRAMDriver.roseSymbols!3 29-Jan-85 22:16:23 PST CacheMInterfaceMRAMDriver.MRAMDriver.rosePorts!3 29-Jan-85 22:16:18 PST CacheMInterfaceMRAMDriver.roseLoad!3 29-Jan-85 22:16:24 PST +CacheMInterfaceMEntryCtl.bcd!12 01-Feb-85 08:12:53 PST CacheMInterfaceMEntryCtl.roseSymbols!3 30-Jan-85 08:50:36 PST CacheMInterfaceMEntryCtl.MEntryCtl.rosePorts!3 30-Jan-85 08:50:21 PST CacheMInterfaceMEntryCtl.roseLoad!3 30-Jan-85 08:50:36 PST +CacheMInterfaceMSequencer.bcd!13 01-Feb-85 08:12:16 PST CacheMInterfaceMSequencer.roseSymbols!4 29-Jan-85 21:38:17 PST CacheMInterfaceMSequencer.MSequencer.rosePorts!4 29-Jan-85 21:38:02 PST CacheMInterfaceMSequencer.roseLoad!4 29-Jan-85 21:38:17 PST +CacheMInterfaceMPads.bcd!11 01-Feb-85 08:12:39 PST CacheMInterfaceMPads.roseSymbols!2 29-Jan-85 21:39:32 PST CacheMInterfaceMPads.MPads.rosePorts!2 29-Jan-85 21:39:25 PST CacheMInterfaceMPads.roseLoad!2 29-Jan-85 21:39:33 PST +CacheMInterfaceMROM.bcd!4 29-Jan-85 21:39:07 PST CacheMInterfaceMROM.roseSymbols!4 29-Jan-85 21:38:59 PST CacheMInterfaceMROM.MROM.rosePorts!4 29-Jan-85 21:38:44 PST CacheMInterfaceMROM.roseLoad!4 29-Jan-85 21:38:59 PST +CachePInterface.bcd!11 01-Feb-85 08:11:44 PST CachePInterface.roseSymbols!2 30-Jan-85 08:49:23 PST CachePInterface.PInterface.rosePorts!2 30-Jan-85 08:49:13 PST CachePInterface.roseLoad!2 30-Jan-85 08:49:24 PST +CachePInterfacePCAMDriver.bcd!2 29-Jan-85 22:16:10 PST CachePInterfacePCAMDriver.roseSymbols!2 29-Jan-85 22:16:02 PST CachePInterfacePCAMDriver.PCAMDriver.rosePorts!2 29-Jan-85 22:15:58 PST CachePInterfacePCAMDriver.roseLoad!2 29-Jan-85 22:16:03 PST +CachePInterfacePCtl.bcd!11 01-Feb-85 08:11:34 PST CachePInterfacePCtl.roseSymbols!2 29-Jan-85 21:37:30 PST CachePInterfacePCtl.PCtl.rosePorts!2 29-Jan-85 21:37:20 PST CachePInterfacePCtl.roseLoad!2 29-Jan-85 21:37:30 PST +CachePInterfacePRAMDriver.bcd!11 01-Feb-85 08:11:21 PST CachePInterfacePRAMDriver.roseSymbols!2 29-Jan-85 22:15:45 PST CachePInterfacePRAMDriver.PRAMDriver.rosePorts!2 29-Jan-85 22:15:40 PST CachePInterfacePRAMDriver.roseLoad!2 29-Jan-85 22:15:45 PST +CachePInterfacePPads.bcd!11 01-Feb-85 08:11:28 PST CachePInterfacePPads.roseSymbols!2 29-Jan-85 21:34:11 PST CachePInterfacePPads.PPads.rosePorts!2 29-Jan-85 21:34:06 PST CachePInterfacePPads.roseLoad!2 29-Jan-85 21:34:11 PST +CacheMicroMachineImpl.bcd!1 12-Jul-84 17:16:39 PDT +CacheMicroCodeA.bcd!2 26-Jul-84 19:12:54 PDT +CacheMicroCodeB.bcd!3 27-Jul-84 17:37:44 PDT +CacheMicroCodeC.bcd!2 26-Jul-84 19:12:37 PDT +CacheMicroCodeD.bcd!3 27-Jul-84 12:13:57 PDT +CacheMicroCodeE.bcd!2 26-Jul-84 19:37:53 PDT Directory [Indigo]NewCache>Rosemary> Cache.cm!6 05-Sep-85 16:50:59 PDT Cache.cmOld!1 29-Jan-85 19:32:17 PST CacheUpdate.cm!3 26-Jul-84 17:49:25 PDT CacheTranslate.cm!1 03-May-84 10:29:30 PDT CacheCompile.cm!1 03-May-84 10:30:32 PDT CacheOps.mesa!3 03-Jul-84 16:04:51 PDT CacheOpsImpl.mesa!3 29-Jul-85 13:52:18 PDT CacheTester.mesa!7 01-Feb-85 09:15:05 PST +CacheTester.bcd!12 01-Feb-85 09:15:19 PST CacheTesterA.mesa!1 26-Jul-84 19:19:04 PDT +CacheTesterA.bcd!11 01-Feb-85 09:36:56 PST CacheTesterB.mesa!3 01-Feb-85 09:36:10 PST +CacheTesterB.bcd!10 01-Feb-85 09:36:17 PST Cache.rose!15 09-Sep-85 16:18:38 PDT Cache.mesa!18 23-Sep-85 15:29:48 PDT CacheImpl.mesa!10 23-Sep-85 15:29:46 PDT CacheEntries.rose!4 01-Feb-85 09:49:05 PST CacheEntries.mesa!5 01-Feb-85 09:49:25 PST CacheEntry.rose!13 01-Feb-85 09:26:56 PST CacheEntry.mesa!4 01-Feb-85 09:27:32 PST CacheMInterface.rose!8 01-Feb-85 09:19:18 PST CacheMInterface.mesa!5 01-Feb-85 09:20:13 PST CacheMInterfaceMCAMDriver.rose!7 29-Jan-85 22:14:50 PST CacheMInterfaceMCAMDriver.mesa!2 29-Jan-85 22:15:25 PST CacheMInterfaceMRAMDriver.rose!8 29-Jan-85 22:14:47 PST CacheMInterfaceMRAMDriver.mesa!3 29-Jan-85 22:16:23 PST CacheMInterfaceMEntryCtl.rose!10 30-Jan-85 08:50:09 PST CacheMInterfaceMEntryCtl.mesa!3 30-Jan-85 08:50:34 PST CacheMInterfaceMSequencer.rose!9 29-Jan-85 21:37:09 PST CacheMInterfaceMSequencer.mesa!4 29-Jan-85 21:38:15 PST CacheMInterfaceMPads.rose!4 29-Jan-85 21:32:03 PST CacheMInterfaceMPads.mesa!2 29-Jan-85 21:39:31 PST CacheMInterfaceMROM.rose!8 29-Jan-85 21:31:30 PST CacheMInterfaceMROM.mesa!4 29-Jan-85 21:38:57 PST CachePInterface.rose!5 30-Jan-85 08:48:36 PST CachePInterface.mesa!2 30-Jan-85 08:49:22 PST CachePInterfacePCAMDriver.rose!2 29-Jan-85 22:14:48 PST CachePInterfacePCAMDriver.mesa!2 29-Jan-85 22:16:02 PST CachePInterfacePCtl.rose!4 29-Jan-85 21:37:11 PST CachePInterfacePCtl.mesa!2 29-Jan-85 21:37:28 PST CachePInterfacePRAMDriver.rose!2 29-Jan-85 22:14:49 PST CachePInterfacePRAMDriver.mesa!2 29-Jan-85 22:15:44 PST CachePInterfacePPads.rose!2 29-Jan-85 21:29:35 PST CachePInterfacePPads.mesa!2 29-Jan-85 21:34:10 PST CacheMicroMachine.mesa!2 29-Jun-84 16:27:56 PDT +CacheMicroMachine.bcd!1 29-Jun-84 16:28:05 PDT CacheMicroMachineImpl.mesa!3 12-Jul-84 17:16:28 PDT CacheMicroCodeA.mesa!10 26-Jul-84 19:05:58 PDT CacheMicroCodeB.mesa!8 27-Jul-84 17:05:09 PDT CacheMicroCodeC.mesa!4 26-Jul-84 18:58:36 PDT CacheMicroCodeD.mesa!8 27-Jul-84 12:13:45 PDT CacheMicroCodeE.mesa!2 26-Jul-84 19:37:44 PDT MicroAnalysis.cm!1 19-Mar-84 19:18:30 PST Directory [Indigo]NewCache>Documentation> CacheROM.sil!1 30-Mar-84 17:19:17 PST MCtlPipe.sil!1 05-Apr-84 18:45:16 PST MCtlBlock.sil!1 10-Apr-84 17:33:37 PST RoseComplaints.tioga!1 01-May-84 16:16:52 PDT DragonDetails.tioga!1 31-May-84 18:16:00 PDT Exports Imports [Indigo]Top>DragonBasics.df Of > Using [DragonImpl.bcd, HexDisplayer.bcd] Exports Imports [Rosemary]3.1>Rosemary.df Of > Using [Rosemary.bcd, BitOpsImpl.bcd] Exports Imports [Cedar]Top>Cucumber.df Of > Using [Cucumber.bcd] Exports Imports [Cedar]Top>ViewerIO.df Of > Using [ViewerIO.bcd] Imports [Indigo]Top>DragonBasics.df Of > Using [Dragon.bcd, Dragon.mesa] Imports [Rosemary]3.1>Rosemary.df Of > Using [BitOps.bcd, BitSwOps.bcd, EnumTypes.bcd, Mnemonics.bcd, NumTypes.bcd, RoseCreate.bcd, RoseEventsImpl.bcd, RoseRun.bcd, RoseTypes.bcd, SwitchTypes.bcd] Imports [Cedar]Top>BasicPackages.df Of > Using [Random.bcd] Imports [Cedar]Top>IO.df Of > Using [Convert.bcd, IO.bcd] Imports [Cedar]Top>FS.df Of > Using [FS.bcd] Imports [Cedar]Top>MesaRuntime.df Of > Using [Basics.bcd] Imports [Cedar]Top>PrintTV.df Of > Using [PrintTV.bcd] Imports [Cedar]Top>Rope.df Of > Using [Rope.bcd, RefText.bcd] Imports [Cedar]Top>SafeStorage.df Of > Using [Atom.bcd]