circuit[Lambda _ 1, Temp _ 100] = { Vdd: node; ! ThymeBasics ! CMOS2.0u100C powerSupply: voltage[Vdd, Gnd] = 5.0; ?: Stray[Vdd| apD_40, ppD_28, anD_32, pnD_32, aM_199, pM_132]; n1: node; ?: Stray[Gnd| aM_193, pM_130, anD_88, pnD_60]; out: node; ?: Stray[out| anD_20, pnD_14, aM_62, pM_46, apD_20, ppD_14]; slowout: node; ?: Stray[slowout| anD_20, pnD_14, aM_62, pM_46, apD_20, ppD_14]; in: node; ?: Stray[in| aP_60, pP_52]; n2: node; slowmatch: node; ?: Stray[slowmatch| anD_24, pnD_16, aM_86, pM_60, aP_99, pP_98]; match: node; ?: Stray[match| aP_99, pP_98, anD_24, pnD_16, aM_89, pM_62]; Q1: ETran[match,out,Gnd]; Q2: CTran[match,Vdd,out]; Q3: CTran[slowmatch,Vdd,slowout]; Q4: ETran[slowmatch,slowout,Gnd]; Q5: ETran[in,match,Gnd| W_6]; Q6: ETran[in,Gnd,slowmatch| L_4]; ?: capacitor[match, Gnd] = 1.0pF; ?: capacitor[slowmatch, Gnd] = 1.0pF; ?: RectWave[in | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 0ns]; }; ic[match _ 5V, slowmatch _ 5V]; PLOT["CMOS TestDCacheArray (2 microns, 100 C)", :1ns, -1, 6, powerSupply^: -1mA, in, match, slowmatch, out, slowout]; RUN[tMax _ 50ns]; []<>TestSlowMatch.thy, Written by Spinifex, March 4, 1985 4:58:07 pm PST Last Edited by: Sindhu, March 4, 1985 4:59:37 pm PST -- ALIAS[ n1, n1] --  "Cedar" styleJHJ4unit##K K KsK%b&Icode>LL L.LGLOL%L LQLILLL!L!LL!LL!L%LYLLLLLJkkuJLZ