andout: node; ?: Stray[andout| anD�, pnD�, apD�, ppD�, aM�, pM�, aP�, pP�];

nD: node; ?: Stray[nD| anD�, pnD�, apD�, ppD�, aM�, pM�, aP�, pP�];

-- ALIAS[ n1, n1] --

n1: node;

n2: node; ?: Stray[n2| anD�, pnD𡤆];

n3: node; ?: Stray[n3| anD�, pnD�, apD�, ppD�, aM�, pM�, aP�, pP�];

n4: node; ?: Stray[n4| anD�, pnD𡤈];

clock: node; ?: Stray[clock| aP�, pP�];

?: Stray[Vdd| apD�, ppD�, anD�, pnD�, aM�, pM�];

n5: node; ?: Stray[n5| anD�, pnD�, aP�, pP�, aM�, pM�, apD�, ppD�];

?: Stray[Gnd| anD�, pnD�, aP�, pP�, aM�, pM�];

match: node; ?: Stray[match| anD�, pnD�, aM�, pM�, aP�, pP�];

D: node; ?: Stray[D| anD�, pnD�, aP�, pP�, aM�, pM�, apD�, ppD�];

Q1: ETran[D,nD,Gnd];

Q2: ETran[andout,D,Gnd| W𡤈];

Q3: CTran[n3,Vdd,andout];

Q4: ETran[nD,D,n2];

Q5: ETran[n3,andout,Gnd];

Q6: CTran[match,Vdd,n3];

Q7: ETran[clock,n3,n4];

Q8: ETran[n5,n5,Gnd];

Q9: CTran[Gnd,Vdd,n5| W𡤃, L𡤈];

Q10: CTran[nD,Vdd,D| W𡤃, L𡤈];

Q11: ETran[n5,n2,Gnd];

Q12: CTran[D,Vdd,nD];

Q13: ETran[match,Gnd,n4];

Q14: CTran[clock,Vdd,n3];

Q15: CTran[clock,Vdd,D];

Q16: ETran[nD,match,Gnd| W𡤃];

?: capacitor[match, Gnd] = .5pF;

?: RectWave[clock | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 5ns];

};

ic[match ← 5V];

PLOT["CMOS TestKillEntry .5 pf match 3/2 pd (2 microns, 100 C)", :1ns, -1, 6, clock, match, D, nD, andout];

RUN[tMax ← 50ns];