-- ALIAS[ n1, n1] --

n1: node; ?: Stray[n1| anD�, pnD�, aM�, pM�];

?: Stray[Gnd| anD�, pnD�, aM�, pM�];

n2: node; ?: Stray[n2| aM2�, pM2�];

n3: node; ?: Stray[n3| aM2�, pM2�];

n4: node; ?: Stray[n4| aP�, pP�, anD�, pnD�];

D: node; ?: Stray[D| anD�, pnD�, aP�, pP�];

$D/nM$: node; ?: Stray[$D/nM$| aM�, pM�, anD�, pnD�];

n5: node; ?: Stray[n5| aP�, pP�, anD�, pnD�];

$nD/M$: node; ?: Stray[$nD/M$| anD�, pnD�, aM�, pM�];

mAccess: node; ?: Stray[mAccess| aP�, pP�];

match: node; ?: Stray[match| anD�, pnD�, aP�, pP�];

n6: node; ?: Stray[n6| aM2�, pM2�];

bit: node; ?: Stray[bit| anD�, pnD�, aM�, pM�];

nbit: node; ?: Stray[nbit| anD�, pnD�, aM�, pM�];

$Q-12$: node; ?: Stray[$Q-12$| anD�, pnD�, aP�, pP�];

nQ: node; ?: Stray[nQ| aP�, pP�, anD�, pnD�];

Q1: ETran[n4,Gnd,D| W𡤈];

Q2: ETran[mAccess,$nD/M$,n4];

Q3: ETran[mAccess,$D/nM$,D];

Q4: ETran[n5,match,Gnd| W𡤆];

Q5: ETran[D,n4,Gnd| W𡤈];

Q6: ETran[D,$D/nM$,n5];

Q7: ETran[n4,$nD/M$,n5];

Q8: ETran[match,bit,$Q-12$];

Q9: ETran[match,nbit,nQ];

Q10: ETran[nQ,n1,$Q-12$| W𡤇];

Q11: ETran[$Q-12$,nQ,n1| W𡤇];

?: capacitor[match, Gnd] = 0.9pF;

?: capacitor[bit, Gnd] = 1.0pF;

?: capacitor[nbit, Gnd] = 1.0pF;

?: RectWave[$D/nM$ | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 0ns];

};

ic[D ← 5V, match ← 5V, Q ← 5V, bit ← 5V, nbit ← 5V];

PLOT["CMOS src (2 microns, 100 C)", :1ns, -1, 6, powerSupply^: -1mA, match, $D/nM$, bit, nbit];

RUN[tMax ← 50ns];