
<<[]<>TestDCacheArray.thy, Written by Spinifex, March 4, 1985 5:38:40 pm PST>>
<<Last Edited by: Sindhu, March 4, 1985 5:42:59 pm PST>>
circuit[Lambda _ 1, Temp _ 100] = {
Vdd: node;
! ThymeBasics
! CMOS2.0u100C
powerSupply: voltage[Vdd, Gnd] = 5.0;

    <<-- ALIAS[ n1, n1] -->>
    n1: node;
    enable: node; ?: Stray[enable| aP_138, pP_142];
    ?: Stray[Gnd| anD_256, pnD_155, aM_1156, pM_684];
    ?: Stray[Vdd| apD_218, ppD_132, anD_112, pnD_112, aM_1085, pM_702];
    daccess: node; ?: Stray[daccess| anD_32, pnD_20, apD_62, ppD_35, aM_75, pM_54, aP_126, pP_126];
    n2: node; ?: Stray[n2| apD_38, ppD_30, anD_19, pnD_15, aP_154, pP_150, aM_169, pM_116];
    mQ: node; ?: Stray[mQ| anD_60, pnD_46, aP_92, pP_96];
    $D/nM$: node; ?: Stray[$D/nM$| aM_192, pM_104, anD_40, pnD_28];
    mAccess: node; ?: Stray[mAccess| aP_50, pP_54];
    DQ: node; ?: Stray[DQ| anD_54, pnD_41, aP_34, pP_38];
    match: node; ?: Stray[match| anD_54, pnD_46, aP_174, pP_178];
    n3: node; ?: Stray[n3| anD_6, pnD_4];
    nslowmatch: node; ?: Stray[nslowmatch| anD_20, pnD_14, apD_20, ppD_14, aM_69, pM_50, aP_178, pP_178];
    n4: node;
    n5: node; ?: Stray[n5| aM2_100, pM2_58];
    bit: node; ?: Stray[bit| anD_20, pnD_14, aM_180, pM_98];
    nbit: node; ?: Stray[nbit| anD_20, pnD_14, aM_180, pM_98];
    nDQ: node; ?: Stray[nDQ| aP_34, pP_38, anD_55, pnD_43];
    nmQ: node; ?: Stray[nmQ| anD_60, pnD_44, aP_64, pP_68];
    n6: node; ?: Stray[n6| aP_42, pP_46, anD_34, pnD_34];
    n7: node; ?: Stray[n7| anD_8, pnD_8];
    $nD/M$: node; ?: Stray[$nD/M$| anD_68, pnD_50, aM_337, pM_200, apD_62, ppD_35];
    slowmatch: node; ?: Stray[slowmatch| aP_116, pP_112, aM_54, pM_40, anD_20, pnD_14];
    nenable: node; ?: Stray[nenable| aP_54, pP_44];
    Q1: ETran[daccess,nbit,nDQ];
    Q2: CTran[n2,Vdd,daccess| W_25];
    Q3: ETran[mAccess,$nD/M$,nmQ];
    Q4: ETran[mAccess,$D/nM$,mQ];
    Q5: ETran[mQ,nmQ,Gnd| W_8];
    Q6: ETran[mQ,$D/nM$,n6];
    Q7: ETran[nDQ,Gnd,DQ| W_7];
    Q8: ETran[DQ,nDQ,Gnd| W_7];
    Q9: ETran[match,n2,n3| W_3];
    Q10: ETran[nslowmatch,n3,Gnd| W_3];
    Q11: CTran[match,Vdd,n2| W_3];
    Q12: CTran[nslowmatch,Vdd,n2| W_3];
    Q13: ETran[n2,daccess,Gnd| W_10];
    Q14: ETran[daccess,bit,DQ];
    Q15: ETran[n6,match,Gnd| W_6];
    Q16: ETran[enable,$nD/M$,Gnd| W_10];
    Q17: ETran[nmQ,Gnd,mQ| W_8];
    Q18: ETran[nmQ,n7,n6];
    Q19: ETran[slowmatch,nslowmatch,Gnd];
    Q20: CTran[slowmatch,Vdd,nslowmatch];
    Q21: CTran[enable,Vdd,$nD/M$| W_25];
    Q22: ETran[nenable,slowmatch,Gnd| L_4];

    ?: capacitor[match, Gnd] = 1.0pF;
    ?: capacitor[slowmatch, Gnd] = 1.0pF;
    ?: capacitor[$nD/M$, Gnd] = 5.3pF;
    ?: capacitor[bit, Gnd] = 3.0pF;
    ?: capacitor[nbit, Gnd] = 3.0pF;
    ?: voltage[$D/nM$, Gnd] = 0.0V;
    ?: voltage[mAccess, Gnd] = 0.0V;
    ?: RectWave[enable | OnLevel _ 0V, OffLevel _ 5V, period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 0ns];

    };

    ic[mQ _ 5V, nmQ _ 0V, DQ _ 5V, nDQ _ 0V, bit _5V, nbit _ 5V, match _ 5V, slowmatch _ 5V, nslowmatch _ 0V];
PLOT["CMOS TestDCacheArray (2 microns, 100 C)", :1ns, -1, 6, powerSupply^: -1mA, enable, $nD/M$, match, nslowmatch, daccess, nbit];
RUN[tMax _ 50ns];