-- ALIAS[ n1, n1] --

n1: node;

enable: node; ?: Stray[enable| aP�, pP�];

?: Stray[Gnd| anD�, pnD�, aM�, pM�];

?: Stray[Vdd| apD�, ppD�, anD�, pnD�, aM�, pM�];

daccess: node; ?: Stray[daccess| anD�, pnD�, apD�, ppD�, aM�, pM�, aP�, pP�];

n2: node; ?: Stray[n2| apD�, ppD�, anD�, pnD�, aP�, pP�, aM�, pM�];

mQ: node; ?: Stray[mQ| anD�, pnD�, aP�, pP�];

$D/nM$: node; ?: Stray[$D/nM$| aM�, pM�, anD�, pnD�];

mAccess: node; ?: Stray[mAccess| aP�, pP�];

DQ: node; ?: Stray[DQ| anD�, pnD�, aP�, pP�];

match: node; ?: Stray[match| anD�, pnD�, aP�, pP�];

n3: node; ?: Stray[n3| anD𡤆, pnD𡤄];

nslowmatch: node; ?: Stray[nslowmatch| anD�, pnD�, apD�, ppD�, aM�, pM�, aP�, pP�];

n4: node;

n5: node; ?: Stray[n5| aM2�, pM2�];

bit: node; ?: Stray[bit| anD�, pnD�, aM�, pM�];

nbit: node; ?: Stray[nbit| anD�, pnD�, aM�, pM�];

nDQ: node; ?: Stray[nDQ| aP�, pP�, anD�, pnD�];

nmQ: node; ?: Stray[nmQ| anD�, pnD�, aP�, pP�];

n6: node; ?: Stray[n6| aP�, pP�, anD�, pnD�];

n7: node; ?: Stray[n7| anD𡤈, pnD𡤈];

$nD/M$: node; ?: Stray[$nD/M$| anD�, pnD�, aM�, pM�, apD�, ppD�];

slowmatch: node; ?: Stray[slowmatch| aP�, pP�, aM�, pM�, anD�, pnD�];

nenable: node; ?: Stray[nenable| aP�, pP�];

Q1: ETran[daccess,nbit,nDQ];

Q2: CTran[n2,Vdd,daccess| W�];

Q3: ETran[mAccess,$nD/M$,nmQ];

Q4: ETran[mAccess,$D/nM$,mQ];

Q5: ETran[mQ,nmQ,Gnd| W𡤈];

Q6: ETran[mQ,$D/nM$,n6];

Q7: ETran[nDQ,Gnd,DQ| W𡤇];

Q8: ETran[DQ,nDQ,Gnd| W𡤇];

Q9: ETran[match,n2,n3| W𡤃];

Q10: ETran[nslowmatch,n3,Gnd| W𡤃];

Q11: CTran[match,Vdd,n2| W𡤃];

Q12: CTran[nslowmatch,Vdd,n2| W𡤃];

Q13: ETran[n2,daccess,Gnd| W�];

Q14: ETran[daccess,bit,DQ];

Q15: ETran[n6,match,Gnd| W𡤆];

Q16: ETran[enable,$nD/M$,Gnd| W�];

Q17: ETran[nmQ,Gnd,mQ| W𡤈];

Q18: ETran[nmQ,n7,n6];

Q19: ETran[slowmatch,nslowmatch,Gnd];

Q20: CTran[slowmatch,Vdd,nslowmatch];

Q21: CTran[enable,Vdd,$nD/M$| W�];

Q22: ETran[nenable,slowmatch,Gnd| L𡤄];

?: capacitor[match, Gnd] = 1.0pF;

?: capacitor[slowmatch, Gnd] = 1.0pF;

?: capacitor[$nD/M$, Gnd] = 5.3pF;

?: capacitor[bit, Gnd] = 3.0pF;

?: capacitor[nbit, Gnd] = 3.0pF;

?: voltage[$D/nM$, Gnd] = 0.0V;

?: voltage[mAccess, Gnd] = 0.0V;

?: RectWave[enable | OnLevel ← 0V, OffLevel ← 5V, period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 0ns];

};

ic[mQ ← 5V, nmQ ← 0V, DQ ← 5V, nDQ ← 0V, bit 𡤅V, nbit ← 5V, match ← 5V, slowmatch ← 5V, nslowmatch ← 0V];

PLOT["CMOS TestDCacheArray (2 microns, 100 C)", :1ns, -1, 6, powerSupply^: -1mA, enable, $nD/M$, match, nslowmatch, daccess, nbit];

RUN[tMax ← 50ns];