DIRECTORY AlpsBool, MCCtl; MCMicrocode: CEDAR PROGRAM IMPORTS AlpsBool, MCCtl EXPORTS MCCtl = BEGIN OPEN AlpsBool, MCCtl; Microcode: PUBLIC PROC [table: TableOfVariables] = BEGIN CtlRPVxAB: Expression _ DefaultDontCare[]; CtlVPVxAB: Expression _ DefaultDontCare[]; arrayAdrsSelPBusxBA: Expression _ false; ResetxBA: Expression _ false; setRefxAB: Expression _ false; matchValidxAB: Expression _ false; wtVictimRPVxAB: Expression _ false; wtMatchingRPVxAB: Expression _ false; wtAddressedRPVxAB: Expression _ false; VInSelVBusxAB: Expression _ false; ldAdrsInLinexAB: Expression _ false; VSelArrayxAB: Expression _ false; accessMatchingCAMxAB: Expression _ false; accessAddressedCAMxAB: Expression _ false; ldMatchxBA: Expression _ false; killAllLinesxAB: Expression _ false; wtMatchingVPVxAB: Expression _ false; wtAddressedVPVxAB: Expression _ false; PQSelArrayVPandAIDxAB: Expression _ false; ldAIDandVPxAB: Expression _ false; prechCBxBA: Expression _ false; drCBforWritexAB: Expression _ false; drCBforMatchxBA: Expression _ false; prechMatchxAB: Expression _ false; accessMatchingRamxAB: Expression _ false; connectAccessLinesxAB: Expression _ false; ldRPandFlagsxAB: Expression _ false; drRBLinesxAB: Expression _ false; PQSelArrayRPandFlagsxAB: Expression _ false; drMBusxBA: Expression _ false; PSelMBusHi25xAB: Expression _ false; PSelMBusLo25xAB: Expression _ false; BEGIN cond: Expression _ EqualInt[table, "CyclexBA", 0, 1, 0]; END; BEGIN cond: Expression _ EqualInt[table, "CyclexAB", 0, 1, 0]; PSelMBusLo25xAB _ If[table, cond, true, PSelMBusLo25xAB]; ldAIDandVPxAB _ If[table, cond, true, ldAIDandVPxAB]; ldAdrsInLinexAB _ If[table, cond, true, ldAdrsInLinexAB]; prechMatchxAB _ If[table, cond, true, prechMatchxAB]; END; BEGIN opCond: Expression _ And[table, Not[Find[table, "MDataxBA[2]"]], Or[table, EqualInt[table, "MCmdxBA", 0, 3, 8], EqualInt[table, "MCmdxBA", 0, 3, 10], EqualInt[table, "MCmdxBA", 0, 3, 12]]]; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexBA", 0, 1, 1], opCond]; drCBforMatchxBA _ If[table, cond, true, drCBforMatchxBA]; ldMatchxBA _ If[table, cond, true, ldMatchxBA]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexAB", 0, 1, 1], opCond]; matchValidxAB _ If[table, cond, true, matchValidxAB]; accessMatchingRamxAB _ If[table, cond, true, accessMatchingRamxAB]; PQSelArrayRPandFlagsxAB _ If[table, cond, true, PQSelArrayRPandFlagsxAB]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexBA", 0, 1, 2], opCond]; drMBusxBA _ If[table, cond, true, drMBusxBA]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexAB", 0, 1, 2], opCond]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexBA", 0, 1, 3], opCond]; drMBusxBA _ If[table, cond, true, drMBusxBA]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexAB", 0, 1, 3], opCond]; END; END; BEGIN opCond: Expression _ And[table, Not[Find[table, "MDataxBA[2]"]], EqualInt[table, "MCmdxBA", 0, 3, 9]]; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexBA", 0, 1, 1], opCond]; drCBforMatchxBA _ If[table, cond, true, drCBforMatchxBA]; ldMatchxBA _ If[table, cond, true, ldMatchxBA]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexAB", 0, 1, 1], opCond]; PSelMBusHi25xAB _ If[table, cond, true, PSelMBusHi25xAB]; ldRPandFlagsxAB _ If[table, cond, true, ldRPandFlagsxAB]; matchValidxAB _ If[table, cond, true, matchValidxAB]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexBA", 0, 1, 2], opCond]; drMBusxBA _ If[table, cond, true, drMBusxBA]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexAB", 0, 1, 2], Find[table, "arrayMatchxAB"], opCond]; drCBforWritexAB _ If[table, cond, true, drCBforWritexAB]; drRBLinesxAB _ If[table, cond, true, drRBLinesxAB]; connectAccessLinesxAB _ If[table, cond, true, connectAccessLinesxAB]; accessMatchingCAMxAB _ If[table, cond, true, accessMatchingCAMxAB]; CtlRPVxAB _ If[table, cond, true, CtlRPVxAB]; wtMatchingRPVxAB _ If[table, cond, true, wtMatchingRPVxAB]; CtlVPVxAB _ If[table, cond, true, CtlVPVxAB]; wtMatchingVPVxAB _ If[table, cond, true, wtMatchingVPVxAB]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexAB", 0, 1, 2], Not[Find[table, "arrayMatchxAB"]], opCond]; drCBforWritexAB _ If[table, cond, true, drCBforWritexAB]; drRBLinesxAB _ If[table, cond, true, drRBLinesxAB]; connectAccessLinesxAB _ If[table, cond, true, connectAccessLinesxAB]; accessAddressedCAMxAB _ If[table, cond, true, accessAddressedCAMxAB]; wtVictimRPVxAB _ If[table, cond, true, wtVictimRPVxAB]; CtlVPVxAB _ If[table, cond, true, CtlVPVxAB]; wtAddressedVPVxAB _ If[table, cond, true, wtAddressedVPVxAB]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexBA", 0, 1, 3], opCond]; drMBusxBA _ If[table, cond, true, drMBusxBA]; END; BEGIN cond: Expression _ And[table, EqualInt[table, "CyclexAB", 0, 1, 3], opCond]; END; END; AddOutput[table, NEW[OutputRec _ [expr: CtlRPVxAB, name: "CtlRPVxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: CtlVPVxAB, name: "CtlVPVxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: arrayAdrsSelPBusxBA, name: "arrayAdrsSelPBusxBA"]]]; AddOutput[table, NEW[OutputRec _ [expr: ResetxBA, name: "ResetxBA"]]]; AddOutput[table, NEW[OutputRec _ [expr: setRefxAB, name: "setRefxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: matchValidxAB, name: "matchValidxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: wtVictimRPVxAB, name: "wtVictimRPVxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: wtMatchingRPVxAB, name: "wtMatchingRPVxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: wtAddressedRPVxAB, name: "wtAddressedRPVxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: VInSelVBusxAB, name: "VInSelVBusxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: ldAdrsInLinexAB, name: "ldAdrsInLinexAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: VSelArrayxAB, name: "VSelArrayxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: accessMatchingCAMxAB, name: "accessMatchingCAMxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: accessAddressedCAMxAB, name: "accessAddressedCAMxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: ldMatchxBA, name: "ldMatchxBA"]]]; AddOutput[table, NEW[OutputRec _ [expr: killAllLinesxAB, name: "killAllLinesxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: wtMatchingVPVxAB, name: "wtMatchingVPVxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: wtAddressedVPVxAB, name: "wtAddressedVPVxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: PQSelArrayVPandAIDxAB, name: "PQSelArrayVPandAIDxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: ldAIDandVPxAB, name: "ldAIDandVPxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: prechCBxBA, name: "prechCBxBA"]]]; AddOutput[table, NEW[OutputRec _ [expr: drCBforWritexAB, name: "drCBforWritexAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: drCBforMatchxBA, name: "drCBforMatchxBA"]]]; AddOutput[table, NEW[OutputRec _ [expr: PQSelArrayVPandAIDxAB, name: "PQSelArrayVPandAIDxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: drCBforWritexAB, name: "drCBforWritexAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: prechMatchxAB, name: "prechMatchxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: accessMatchingRamxAB, name: "accessMatchingRamxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: connectAccessLinesxAB, name: "connectAccessLinesxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: ldRPandFlagsxAB, name: "ldRPandFlagsxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: drRBLinesxAB, name: "drRBLinesxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: PQSelArrayRPandFlagsxAB, name: "PQSelArrayRPandFlagsxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: drMBusxBA, name: "drMBusxBA"]]]; AddOutput[table, NEW[OutputRec _ [expr: PSelMBusHi25xAB, name: "PSelMBusHi25xAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: PSelMBusLo25xAB, name: "PSelMBusLo25xAB"]]]; END; END. bMCMicrocode.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Created by: Sindhu, June 20, 1985 7:04:53 pm PDT Last Edited by: Sindhu, July 9, 1985 3:20:40 am PDT AID RAM control signals: omit for debug version pnSelMasterxBA: Expression _ DefaultDontCare[]; QSelAIDxAB: Expression _ false; wtAIDxAB: Expression _ false; ldxpnxAB: Expression _ false; Array control signals: Bypass control signals: omit for debug version selBypassPPortxAB: Expression _ DefaultDontCare[]; RSelBypassxBA: Expression _ false; ldBypassResultxBA: Expression _ false; forceInxAB: Expression _ false; forceOutxAB: Expression _ false; MInterface control signals: MCmdSelCmdxBA: Expression _ DefaultDontCare[]; -- omit for debugging version QSelMBuslo10xAB: Expression _ false; omit for debug version Order control signals: omit for debug version QSelOrderxAB: Expression _ false; First the code for cycle 0, the idle cycle: Cycle 0.A pnSelMasterxBA _ If[table, cond, true, pnSelMasterxBA]; Cycle 0.B QSelAIDxAB _ If[table, cond, true, QSelAIDxAB]; wtAIDxAB _ If[table, cond, false, wtAIDxAB]; selBypassPPortxAB _ If[table, cond, true, selBypassPPortxAB]; ReadMapSetRef, ReadMapSetRefSetDirty, and ReadEntry: Cycle 1.A Cycle 1.B QSelOrderxAB _ If[table, cond, true, QSelOrderxAB]; Cycle 2.A ldBypassResultxBA _ If[table, cond, true, ldBypassResultxBA]; RSelBypassxBA _ If[table, cond, true, RSelBypassxBA]; MCmdSelCmdxBA _ If[table, cond, true, MCmdSelCmdxBA]; Cycle 2.B Cycle 3.A ldBypassResultxBA _ If[table, cond, false, ldBypassResultxBA]; RSelBypassxBA _ If[table, cond, true, RSelBypassxBA]; RSelBypassxBA _ If[table, cond, true, RSelBypassxBA]; Cycle 3.B WriteEntry: Cycle 1.A Cycle 1.B QSelMBuslo10xAB _ If[table, cond, true, QSelMBuslo10xAB]; Cycle 2.A ldBypassResultxBA _ If[table, cond, true, ldBypassResultxBA]; RSelBypassxBA _ If[table, cond, true, RSelBypassxBA]; MCmdSelCmdxBA _ If[table, cond, true, MCmdSelCmdxBA]; Cycle 2.B match Cycle 2.B notMatch Cycle 3.A ldBypassResultxBA _ If[table, cond, false, ldBypassResultxBA]; RSelBypassxBA _ If[table, cond, true, RSelBypassxBA]; RSelBypassxBA _ If[table, cond, true, RSelBypassxBA]; Cycle 3.B AddOutput[table, NEW[OutputRec _ [expr: QSelOrderxAB, name: "QSelOrderxAB"]]]; AddOutput[table, NEW[OutputRec _ [expr: MCmdSelCmdxBA, name: "MCmdSelCmdxBA"]]]; AddOutput[table, NEW[OutputRec _ [expr: QSelMBuslo10xAB, name: "QSelMBuslo10xAB"]]]; Êh˜code™Kšœ Ïmœ1™™>Kšœ5™5Kšœ-˜-Kšœ5™5Kšžœ˜—K˜™ Kšž˜KšœL˜LKšžœ˜—Kšžœ˜—K˜™Kšž˜šœ˜Kšœ ˜ Kšœ%˜%—K˜™ Kšž˜KšœL˜LK˜Kšœ9˜9Kšœ/˜/Kšžœ˜—K˜™ Kšž˜KšœL˜LK˜Kšœ9˜9Kšœ9™9Kšœ9˜9Kšœ5˜5Kšžœ˜—K˜™ Kšž˜KšœL˜LK˜Kšœ=™=Kšœ5™5Kšœ-˜-Kšœ5™5Kšžœ˜—K™™Kšž˜Kšœj˜jK˜Kšœ9˜9Kšœ3˜3KšœE˜EKšœC˜CKšœ-˜-Kšœ;˜;Kšœ-˜-Kšœ;˜;Kšžœ˜—K˜™Kšž˜Kšœo˜oK˜Kšœ9˜9Kšœ3˜3KšœE˜EKšœE˜EKšœ7˜7Kšœ-˜-Kšœ=˜=Kšžœ˜—K˜™ Kšž˜KšœL˜LK˜Kšœ>™>Kšœ5™5Kšœ-˜-Kšœ5™5Kšžœ˜—K˜™ Kšž˜KšœL˜LKšžœ˜—K˜Kšžœ˜—K˜Kšœžœ4˜HKšœžœ4˜HKšœžœH˜\Kšœžœ2˜FKšœžœ4˜HKšœžœ<˜PKšœžœ>˜RKšœžœB˜VKšœžœD˜XKšœžœ<˜PKšœžœ@˜TKšœžœ:˜NKšœžœJ˜^KšœžœL˜`Kšœžœ6˜JKšœžœ@˜TKšœžœB˜VKšœžœD˜XKšœžœL˜`Kšœžœ<˜PKšœžœ6˜JKšœžœ@˜TKšœžœ@˜TKšœžœL˜`Kšœžœ@˜TKšœžœ<˜PKšœžœJ˜^KšœžœL˜`Kšœžœ:™NKšœžœ@˜TKšœžœ:˜NKšœžœP˜dKšœžœ<™PKšœžœ4˜HKšœžœ@˜TKšœžœ@˜TKšœžœ@™TK˜Kšžœ˜—K˜Kšžœ˜——…—ž/h