Microcode:
PUBLIC PROC [table: TableOfVariables] =
BEGIN
AID RAM control signals: omit for debug version
pnSelMasterxBA: Expression ← DefaultDontCare[];
QSelAIDxAB: Expression ← false;
wtAIDxAB: Expression ← false;
ldxpnxAB: Expression ← false;
Array control signals:
CtlRPVxAB: Expression ← DefaultDontCare[];
CtlVPVxAB: Expression ← DefaultDontCare[];
arrayAdrsSelPBusxBA: Expression ← false;
ResetxBA: Expression ← false;
setRefxAB: Expression ← false;
matchValidxAB: Expression ← false;
wtVictimRPVxAB: Expression ← false;
wtMatchingRPVxAB: Expression ← false;
wtAddressedRPVxAB: Expression ← false;
VInSelVBusxAB: Expression ← false;
ldAdrsInLinexAB: Expression ← false;
VSelArrayxAB: Expression ← false;
accessMatchingCAMxAB: Expression ← false;
accessAddressedCAMxAB: Expression ← false;
ldMatchxBA: Expression ← false;
killAllLinesxAB: Expression ← false;
wtMatchingVPVxAB: Expression ← false;
wtAddressedVPVxAB: Expression ← false;
PQSelArrayVPandAIDxAB: Expression ← false;
ldAIDandVPxAB: Expression ← false;
prechCBxBA: Expression ← false;
drCBforWritexAB: Expression ← false;
drCBforMatchxBA: Expression ← false;
prechMatchxAB: Expression ← false;
accessMatchingRamxAB: Expression ← false;
connectAccessLinesxAB: Expression ← false;
ldRPandFlagsxAB: Expression ← false;
drRBLinesxAB: Expression ← false;
PQSelArrayRPandFlagsxAB: Expression ← false;
Bypass control signals: omit for debug version
selBypassPPortxAB: Expression ← DefaultDontCare[];
RSelBypassxBA: Expression ← false;
ldBypassResultxBA: Expression ← false;
forceInxAB: Expression ← false;
forceOutxAB: Expression ← false;
MInterface control signals:
MCmdSelCmdxBA: Expression ← DefaultDontCare[]; -- omit for debugging version
drMBusxBA: Expression ← false;
PSelMBusHi25xAB: Expression ← false;
PSelMBusLo25xAB: Expression ← false;
QSelMBuslo10xAB: Expression ← false; omit for debug version
Order control signals: omit for debug version
QSelOrderxAB: Expression ← false;
First the code for cycle 0, the idle cycle:
Cycle 0.A
BEGIN
cond: Expression ← EqualInt[table, "CyclexBA", 0, 1, 0];
pnSelMasterxBA ← If[table, cond, true, pnSelMasterxBA];
END;
Cycle 0.B
BEGIN
cond: Expression ← EqualInt[table, "CyclexAB", 0, 1, 0];
PSelMBusLo25xAB ← If[table, cond, true, PSelMBusLo25xAB];
ldAIDandVPxAB ← If[table, cond, true, ldAIDandVPxAB];
QSelAIDxAB ← If[table, cond, true, QSelAIDxAB];
wtAIDxAB ← If[table, cond, false, wtAIDxAB];
ldAdrsInLinexAB ← If[table, cond, true, ldAdrsInLinexAB];
prechMatchxAB ← If[table, cond, true, prechMatchxAB];
selBypassPPortxAB ← If[table, cond, true, selBypassPPortxAB];
END;
ReadMapSetRef, ReadMapSetRefSetDirty, and ReadEntry:
BEGIN
opCond: Expression ← And[table,
Not[Find[table, "MDataxBA[2]"]],
Or[table,
EqualInt[table, "MCmdxBA", 0, 3, 8],
EqualInt[table, "MCmdxBA", 0, 3, 10],
EqualInt[table, "MCmdxBA", 0, 3, 12]]];
Cycle 1.A
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexBA", 0, 1, 1], opCond];
drCBforMatchxBA ← If[table, cond, true, drCBforMatchxBA];
ldMatchxBA ← If[table, cond, true, ldMatchxBA];
END;
Cycle 1.B
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexAB", 0, 1, 1], opCond];
matchValidxAB ← If[table, cond, true, matchValidxAB];
accessMatchingRamxAB ← If[table, cond, true, accessMatchingRamxAB];
PQSelArrayRPandFlagsxAB ← If[table, cond, true, PQSelArrayRPandFlagsxAB];
QSelOrderxAB ← If[table, cond, true, QSelOrderxAB];
END;
Cycle 2.A
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexBA", 0, 1, 2], opCond];
ldBypassResultxBA ← If[table, cond, true, ldBypassResultxBA];
RSelBypassxBA ← If[table, cond, true, RSelBypassxBA];
drMBusxBA ← If[table, cond, true, drMBusxBA];
MCmdSelCmdxBA ← If[table, cond, true, MCmdSelCmdxBA];
END;
Cycle 2.B
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexAB", 0, 1, 2], opCond];
END;
Cycle 3.A
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexBA", 0, 1, 3], opCond];
ldBypassResultxBA ← If[table, cond, false, ldBypassResultxBA];
RSelBypassxBA ← If[table, cond, true, RSelBypassxBA];
drMBusxBA ← If[table, cond, true, drMBusxBA];
RSelBypassxBA ← If[table, cond, true, RSelBypassxBA];
END;
Cycle 3.B
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexAB", 0, 1, 3], opCond];
END;
END;
WriteEntry:
BEGIN
opCond: Expression ← And[table,
Not[Find[table, "MDataxBA[2]"]],
EqualInt[table, "MCmdxBA", 0, 3, 9]];
Cycle 1.A
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexBA", 0, 1, 1], opCond];
drCBforMatchxBA ← If[table, cond, true, drCBforMatchxBA];
ldMatchxBA ← If[table, cond, true, ldMatchxBA];
END;
Cycle 1.B
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexAB", 0, 1, 1], opCond];
PSelMBusHi25xAB ← If[table, cond, true, PSelMBusHi25xAB];
QSelMBuslo10xAB ← If[table, cond, true, QSelMBuslo10xAB];
ldRPandFlagsxAB ← If[table, cond, true, ldRPandFlagsxAB];
matchValidxAB ← If[table, cond, true, matchValidxAB];
END;
Cycle 2.A
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexBA", 0, 1, 2], opCond];
ldBypassResultxBA ← If[table, cond, true, ldBypassResultxBA];
RSelBypassxBA ← If[table, cond, true, RSelBypassxBA];
drMBusxBA ← If[table, cond, true, drMBusxBA];
MCmdSelCmdxBA ← If[table, cond, true, MCmdSelCmdxBA];
END;
Cycle 2.B match
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexAB", 0, 1, 2], Find[table, "arrayMatchxAB"], opCond];
drCBforWritexAB ← If[table, cond, true, drCBforWritexAB];
drRBLinesxAB ← If[table, cond, true, drRBLinesxAB];
connectAccessLinesxAB ← If[table, cond, true, connectAccessLinesxAB];
accessMatchingCAMxAB ← If[table, cond, true, accessMatchingCAMxAB];
CtlRPVxAB ← If[table, cond, true, CtlRPVxAB];
wtMatchingRPVxAB ← If[table, cond, true, wtMatchingRPVxAB];
CtlVPVxAB ← If[table, cond, true, CtlVPVxAB];
wtMatchingVPVxAB ← If[table, cond, true, wtMatchingVPVxAB];
END;
Cycle 2.B notMatch
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexAB", 0, 1, 2], Not[Find[table, "arrayMatchxAB"]], opCond];
drCBforWritexAB ← If[table, cond, true, drCBforWritexAB];
drRBLinesxAB ← If[table, cond, true, drRBLinesxAB];
connectAccessLinesxAB ← If[table, cond, true, connectAccessLinesxAB];
accessAddressedCAMxAB ← If[table, cond, true, accessAddressedCAMxAB];
wtVictimRPVxAB ← If[table, cond, true, wtVictimRPVxAB];
CtlVPVxAB ← If[table, cond, true, CtlVPVxAB];
wtAddressedVPVxAB ← If[table, cond, true, wtAddressedVPVxAB];
END;
Cycle 3.A
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexBA", 0, 1, 3], opCond];
ldBypassResultxBA ← If[table, cond, false, ldBypassResultxBA];
RSelBypassxBA ← If[table, cond, true, RSelBypassxBA];
drMBusxBA ← If[table, cond, true, drMBusxBA];
RSelBypassxBA ← If[table, cond, true, RSelBypassxBA];
END;
Cycle 3.B
BEGIN
cond: Expression ← And[table, EqualInt[table, "CyclexAB", 0, 1, 3], opCond];
END;
END;
AddOutput[table, NEW[OutputRec ← [expr: CtlRPVxAB, name: "CtlRPVxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: CtlVPVxAB, name: "CtlVPVxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: arrayAdrsSelPBusxBA, name: "arrayAdrsSelPBusxBA"]]];
AddOutput[table, NEW[OutputRec ← [expr: ResetxBA, name: "ResetxBA"]]];
AddOutput[table, NEW[OutputRec ← [expr: setRefxAB, name: "setRefxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: matchValidxAB, name: "matchValidxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: wtVictimRPVxAB, name: "wtVictimRPVxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: wtMatchingRPVxAB, name: "wtMatchingRPVxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: wtAddressedRPVxAB, name: "wtAddressedRPVxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: VInSelVBusxAB, name: "VInSelVBusxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: ldAdrsInLinexAB, name: "ldAdrsInLinexAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: VSelArrayxAB, name: "VSelArrayxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: accessMatchingCAMxAB, name: "accessMatchingCAMxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: accessAddressedCAMxAB, name: "accessAddressedCAMxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: ldMatchxBA, name: "ldMatchxBA"]]];
AddOutput[table, NEW[OutputRec ← [expr: killAllLinesxAB, name: "killAllLinesxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: wtMatchingVPVxAB, name: "wtMatchingVPVxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: wtAddressedVPVxAB, name: "wtAddressedVPVxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: PQSelArrayVPandAIDxAB, name: "PQSelArrayVPandAIDxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: ldAIDandVPxAB, name: "ldAIDandVPxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: prechCBxBA, name: "prechCBxBA"]]];
AddOutput[table, NEW[OutputRec ← [expr: drCBforWritexAB, name: "drCBforWritexAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: drCBforMatchxBA, name: "drCBforMatchxBA"]]];
AddOutput[table, NEW[OutputRec ← [expr: PQSelArrayVPandAIDxAB, name: "PQSelArrayVPandAIDxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: drCBforWritexAB, name: "drCBforWritexAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: prechMatchxAB, name: "prechMatchxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: accessMatchingRamxAB, name: "accessMatchingRamxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: connectAccessLinesxAB, name: "connectAccessLinesxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: QSelOrderxAB, name: "QSelOrderxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: ldRPandFlagsxAB, name: "ldRPandFlagsxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: drRBLinesxAB, name: "drRBLinesxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: PQSelArrayRPandFlagsxAB, name: "PQSelArrayRPandFlagsxAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: MCmdSelCmdxBA, name: "MCmdSelCmdxBA"]]];
AddOutput[table, NEW[OutputRec ← [expr: drMBusxBA, name: "drMBusxBA"]]];
AddOutput[table, NEW[OutputRec ← [expr: PSelMBusHi25xAB, name: "PSelMBusHi25xAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: PSelMBusLo25xAB, name: "PSelMBusLo25xAB"]]];
AddOutput[table, NEW[OutputRec ← [expr: QSelMBuslo10xAB, name: "QSelMBuslo10xAB"]]];
END;