DIRECTORY Core, CoreClasses, CoreFlat, CoreFrame, CoreLibrary, CoreName, CoreOps, CoreProperties, CoreWire, IFUCoreCells, IFUCoreDrive, IFUSim, IFUTest, Ports, Rosemary, RosemaryUser;

IFUTestLibrary: CEDAR PROGRAM
IMPORTS CoreClasses, CoreFlat, CoreFrame, CoreLibrary, CoreName, CoreOps, CoreProperties, CoreWire, IFUCoreCells, IFUCoreDrive, IFUSim, Ports, Rosemary, RosemaryUser
EXPORTS IFUTest =
BEGIN

ROPE:		TYPE = Core.ROPE;
CellType:	TYPE = Core.CellType;
Wire:		TYPE = Core.Wire;
Signal: SIGNAL = CODE;


TestVectors:		TYPE = REF TestVectorSeq;
TestVectorSeq:	TYPE = RECORD[SEQUENCE size: CARDINAL OF TestRec];
TestRec:			TYPE = RECORD[c0, c1, i0, i1, out: Ports.Level _ X];

GeneralPurposeTest: PROC[name: ROPE, vectors: TestVectors] = {
cell: CellType _ Extract[name];
Simulate[cell, vectors]};

Extract: PROC[name: ROPE] RETURNS[cell: CellType]={
cell _ CoreLibrary.Get[library, name];
};

Simulate: PROC[cell: CellType, vectors: TestVectors, cutLabels: LIST OF ROPE _ NIL] = {
cuts: CoreFlat.CutSet _ CoreFlat.CreateCutSet[labels: cutLabels];
DoSim: PROC[index: CARDINAL] = {
v: TestRec _ vectors[index];
IF (v.c0=X)	# (ctl0=-1)	THEN Signal[];
IF (v.c1=X)	# (ctl1=-1)	THEN Signal[];
IF (v.i0=X)	# (in0=-1) 	THEN Signal[];
IF (v.i1=X)	# (in1=-1)	THEN Signal[];
IF v.c0#X	THEN testerPort[ctl0].l	_ v.c0;
IF v.c1#X	THEN testerPort[ctl1].l	_ v.c1;
IF v.i0#X		THEN testerPort[in0].l	_ v.i0;
IF v.i1#X		THEN testerPort[in1].l	_ v.i1;
Rosemary.Settle[simulation];
IF testerPort[out].l#v.out THEN Signal[]};
ctl0, ctl1, in0, in1, out, VDD, GND: INT;
testerWire:	CoreWire.CWire;
testerPort:		Ports.Port;
simulation:	Rosemary.Simulation;
testerWire	_ [cell.public];
ctl0			_ CoreOps.GetWireIndex[testerWire.w, "0"];
ctl1			_ CoreOps.GetWireIndex[testerWire.w, "1"];
in0			_ CoreOps.GetWireIndex[testerWire.w, "in0"];
in1			_ CoreOps.GetWireIndex[testerWire.w, "in1"];
out			_ CoreOps.GetWireIndex[testerWire.w, "out0"];
VDD			_ CoreOps.GetWireIndex[testerWire.w, "VDD"];
GND			_ CoreOps.GetWireIndex[testerWire.w, "GND"];
IF ctl0#-1 THEN	[]_Ports.InitPort[wire: testerWire.i[ctl0].w, levelType: l, initDrive: force];
IF ctl1#-1 THEN	[]_Ports.InitPort[wire: testerWire.i[ctl1].w, levelType: l, initDrive: force];
IF in0#-1 THEN	[]_Ports.InitPort[wire: testerWire.i[in0].w, levelType: l, initDrive: force];
IF in1#-1 THEN	[]_Ports.InitPort[wire: testerWire.i[in1].w, levelType: l, initDrive: force];
					[]_Ports.InitPort[wire: testerWire.i[out].w, levelType: l, initDrive: none];
IF ctl0#-1 THEN	[]_Ports.InitTesterDrive[wire: testerWire.i[ctl0].w, initDrive: force];
IF ctl1#-1 THEN	[]_Ports.InitTesterDrive[wire: testerWire.i[ctl1].w, initDrive: force];
IF in0#-1 THEN	[]_Ports.InitTesterDrive[wire: testerWire.i[in0].w, initDrive: force];
IF in1#-1 THEN	[]_Ports.InitTesterDrive[wire: testerWire.i[in1].w, initDrive: force];
					[]_Ports.InitTesterDrive[wire: testerWire.i[out].w, initDrive: none];
[ ] _ Rosemary.SetFixedWire[testerWire.w[VDD], H];
[ ] _ Rosemary.SetFixedWire[testerWire.w[GND], L];
testerPort _ Ports.CreatePort[cell, TRUE];
simulation _ Rosemary.Instantiate[cell, testerPort, cuts];
FOR index1: CARDINAL IN [0..vectors.size) DO
DoSim[index1];
ENDLOOP };

TestSAdder: PROC = {
DoSim: PROC[index: CARDINAL] = {
carry:	BOOL	_ ((index/1)	MOD 2) = 1;
ain:	BOOL	_ ((index/2)	MOD 2) = 1;
bin:	BOOL	_ ((index/4)	MOD 2) = 1;
testerPort[cyI].l	_ IF carry	THEN H ELSE L;
testerPort[in0].l	_ IF ain		THEN H ELSE L;
testerPort[in1].l	_ IF bin		THEN H ELSE L;
Rosemary.Settle[simulation];
IF (carry#ain)#(bin#(testerPort[out].l=H)) THEN Signal[];
IF (carry AND (ain OR bin) OR ain AND bin)#(testerPort[cyO].l=H) THEN Signal[]};
cyI, cyO, in0, in1, out, VDD, GND: INT;
testerWire:	CoreWire.CWire;
testerPort:		Ports.Port;
simulation:	Rosemary.Simulation;
cell:			CellType _ Extract["DpAdderSerial"];
testerWire	_ [cell.public];
cyI			_ CoreOps.GetWireIndex[testerWire.w, "in2"];
cyO			_ CoreOps.GetWireIndex[testerWire.w, "out2"];
in0			_ CoreOps.GetWireIndex[testerWire.w, "in0"];
in1			_ CoreOps.GetWireIndex[testerWire.w, "in1"];
out			_ CoreOps.GetWireIndex[testerWire.w, "out0"];
VDD			_ CoreOps.GetWireIndex[testerWire.w, "VDD"];
GND			_ CoreOps.GetWireIndex[testerWire.w, "GND"];
[]_Ports.InitPort[wire: testerWire.i[cyI].w, levelType: l, initDrive: force];
[]_Ports.InitPort[wire: testerWire.i[cyO].w, levelType: l, initDrive: none];
[]_Ports.InitPort[wire: testerWire.i[in0].w, levelType: l, initDrive: force];
[]_Ports.InitPort[wire: testerWire.i[in1].w, levelType: l, initDrive: force];
[]_Ports.InitPort[wire: testerWire.i[out].w, levelType: l, initDrive: none];
[]_Ports.InitTesterDrive[wire: testerWire.i[cyI].w, initDrive: force];
[]_Ports.InitTesterDrive[wire: testerWire.i[cyO].w, initDrive: none];
[]_Ports.InitTesterDrive[wire: testerWire.i[in0].w, initDrive: force];
[]_Ports.InitTesterDrive[wire: testerWire.i[in1].w, initDrive: force];
[]_Ports.InitTesterDrive[wire: testerWire.i[out].w, initDrive: none];
[ ] _ Rosemary.SetFixedWire[testerWire.w[VDD], H];
[ ] _ Rosemary.SetFixedWire[testerWire.w[GND], L];
testerPort _ Ports.CreatePort[cell, TRUE];
simulation _ Rosemary.Instantiate[cell, testerPort];
FOR index1: CARDINAL IN [0..8) DO
FOR index2: CARDINAL IN [0..8) DO -- check for hidden state
DoSim[index1];
DoSim[index2];
ENDLOOP;
ENDLOOP };

TestGPC: PROC[gpLRNeg: BOOL] = {
UpdateDisplay: PROC = {
RosemaryUser.UpdateDisplay[display]};
DisplayAndSignal: PROC = {
RosemaryUser.UpdateDisplay[display];
Signal[]};
gl, pl, cl, gm, pm, cm, gr, pr, cr, VDD, GND: INT;
cell:			CellType;
testerWire:	CoreWire.CWire;
testerPort:		Ports.Port;
simulation:	Rosemary.Simulation;
display:		RosemaryUser.RoseDisplay;
IF gpLRNeg
THEN {
cell			_ CoreLibrary.Get[ library, "DpAdderGPC0", FALSE, LIST["Cry"]];
testerWire	_ [cell.public];
gl		_ CoreOps.GetWireIndex[testerWire.w, "nGL"];
pl		_ CoreOps.GetWireIndex[testerWire.w, "nPL"];
cl		_ CoreOps.GetWireIndex[testerWire.w, "CL"];
gm	_ CoreOps.GetWireIndex[testerWire.w, "GM"];
pm	_ CoreOps.GetWireIndex[testerWire.w, "PM"];
cm	_ CoreOps.GetWireIndex[testerWire.w, "nCM"];
gr		_ CoreOps.GetWireIndex[testerWire.w, "nGR"];
pr		_ CoreOps.GetWireIndex[testerWire.w, "nPR"];
cr		_ CoreOps.GetWireIndex[testerWire.w, "CR"]}
ELSE {
cell			_ CoreLibrary.Get[ library, "DpAdderGPC1", FALSE, LIST["Cry"]];
testerWire	_ [cell.public];
gl		_ CoreOps.GetWireIndex[testerWire.w, "GL"];
pl		_ CoreOps.GetWireIndex[testerWire.w, "PL"];
cl		_ CoreOps.GetWireIndex[testerWire.w, "nCL"];
gm	_ CoreOps.GetWireIndex[testerWire.w, "nGM"];
pm	_ CoreOps.GetWireIndex[testerWire.w, "nPM"];
cm	_ CoreOps.GetWireIndex[testerWire.w, "CM"];
gr		_ CoreOps.GetWireIndex[testerWire.w, "GR"];
pr		_ CoreOps.GetWireIndex[testerWire.w, "PR"];
cr		_ CoreOps.GetWireIndex[testerWire.w, "nCR"]};
VDD	_ CoreOps.GetWireIndex[testerWire.w, "VDD"];
GND	_ CoreOps.GetWireIndex[testerWire.w, "GND"];

[]_Ports.InitPort[wire: testerWire.i[gl].w,		levelType: b,	initDrive: force];
[]_Ports.InitPort[wire: testerWire.i[pl].w,		levelType: b,	initDrive: force];
[]_Ports.InitPort[wire: testerWire.i[cl].w,		levelType: b,	initDrive: none];
[]_Ports.InitPort[wire: testerWire.i[gm].w,	levelType: b,	initDrive: none];
[]_Ports.InitPort[wire: testerWire.i[pm].w,	levelType: b,	initDrive: none];
[]_Ports.InitPort[wire: testerWire.i[cm].w,		levelType: b,	initDrive: force];
[]_Ports.InitPort[wire: testerWire.i[gr].w,		levelType: b,	initDrive: force];
[]_Ports.InitPort[wire: testerWire.i[pr].w,		levelType: b,	initDrive: force];
[]_Ports.InitPort[wire: testerWire.i[cr].w,		levelType: b,	initDrive: none];

[]_Ports.InitTesterDrive[wire: testerWire.i[gl].w,				initDrive: force];
[]_Ports.InitTesterDrive[wire: testerWire.i[pl].w,				initDrive: force];
[]_Ports.InitTesterDrive[wire: testerWire.i[cl].w,				initDrive: none];
[]_Ports.InitTesterDrive[wire: testerWire.i[gm].w,			initDrive: none];
[]_Ports.InitTesterDrive[wire: testerWire.i[pm].w,			initDrive: none];
[]_Ports.InitTesterDrive[wire: testerWire.i[cm].w,			initDrive: force];
[]_Ports.InitTesterDrive[wire: testerWire.i[gr].w,				initDrive: force];
[]_Ports.InitTesterDrive[wire: testerWire.i[pr].w,				initDrive: force];
[]_Ports.InitTesterDrive[wire: testerWire.i[cr].w,				initDrive: none];

[ ] _ Rosemary.SetFixedWire[testerWire.w[VDD], H];
[ ] _ Rosemary.SetFixedWire[testerWire.w[GND], L];
testerPort		_ Ports.CreatePort[cell, TRUE];
simulation	_ Rosemary.Instantiate[cell, testerPort];
display		_ RosemaryUser.DisplayViewer[simulation, cell, "IFU Test", RosemaryUser.DisplayPortLeafWires[cell]];
FOR gL:	BOOL IN BOOL DO
FOR pL:	BOOL IN BOOL DO
FOR gR:	BOOL IN BOOL DO
FOR pR:	BOOL IN BOOL DO
FOR cM:	BOOL IN BOOL DO
gM:	BOOL;
pM:	BOOL;
cL:	BOOL;
cR:	BOOL;
testerPort[gl].b	_  gpLRNeg # gL;
testerPort[pl].b	_  gpLRNeg # pL;
testerPort[gr].b	_  gpLRNeg # gR;
testerPort[pr].b	_  gpLRNeg # pR;
testerPort[cm].b	_  gpLRNeg # cM;
Rosemary.Settle[simulation ! Rosemary.Stop => UpdateDisplay[]];
gM	_ gpLRNeg = testerPort[gm].b;
pM	_ gpLRNeg = testerPort[pm].b;
cL		_ gpLRNeg = testerPort[cl].b;
cR		_ gpLRNeg = testerPort[cr].b;
IF 			cM				# 	cR		THEN DisplayAndSignal[];
IF (gR OR	(cM AND pR))	# 	cL		THEN DisplayAndSignal[];
IF (gL OR	(pL AND gR))	#	gM	THEN DisplayAndSignal[];
IF 			(pL AND pR) 	#	pM	THEN DisplayAndSignal[];
ENDLOOP ENDLOOP ENDLOOP ENDLOOP ENDLOOP };


TestAllSimples: PROC = {
bufVectors:	TestVectors _ NEW[TestVectorSeq[2]];
invVectors:	TestVectors _ NEW[TestVectorSeq[2]];
orVectors:	TestVectors _ NEW[TestVectorSeq[4]];
norVectors:	TestVectors _ NEW[TestVectorSeq[4]];
andVectors:	TestVectors _ NEW[TestVectorSeq[4]];
nandVectors:	TestVectors _ NEW[TestVectorSeq[4]];
xorVectors:	TestVectors _ NEW[TestVectorSeq[4]];
xnorVectors:	TestVectors _ NEW[TestVectorSeq[4]];


bufVectors[0]	_ [i0: L,		i1: X,		out: L];
bufVectors[1]	_ [i0: H,		i1: X,		out: H];

invVectors[0]	_ [i0: L,		i1: X,		out: H];
invVectors[1]	_ [i0: H,		i1: X,		out: L];

orVectors[0]		_ [i0: L,		i1: L,		out: L];
orVectors[1]		_ [i0: L,		i1: H,		out: H];
orVectors[2]		_ [i0: H,		i1: L,		out: H];
orVectors[3]		_ [i0: H,		i1: H,		out: H];

norVectors[0]	_ [i0: L,		i1: L,		out: H];
norVectors[1]	_ [i0: L,		i1: H,		out: L];
norVectors[2]	_ [i0: H,		i1: L,		out: L];
norVectors[3]	_ [i0: H,		i1: H,		out: L];

andVectors[0]	_ [i0: L,		i1: L,		out: L];
andVectors[1]	_ [i0: L,		i1: H,		out: L];
andVectors[2]	_ [i0: H,		i1: L,		out: L];
andVectors[3]	_ [i0: H,		i1: H,		out: H];

nandVectors[0]	_ [i0: L,		i1: L,		out: H];
nandVectors[1]	_ [i0: L,		i1: H,		out: H];
nandVectors[2]	_ [i0: H,		i1: L,		out: H];
nandVectors[3]	_ [i0: H,		i1: H,		out: L];

xorVectors[0]		_ [i0: L,		i1: L,		out: L];
xorVectors[1]		_ [i0: L,		i1: H,		out: H];
xorVectors[2]		_ [i0: H,		i1: L,		out: H];
xorVectors[3]		_ [i0: H,		i1: H,		out: L];

xnorVectors[0]	_ [i0: L,		i1: L,		out: H];
xnorVectors[1]	_ [i0: L,		i1: H,		out: L];
xnorVectors[2]	_ [i0: H,		i1: L,		out: L];
xnorVectors[3]	_ [i0: H,		i1: H,		out: H];

GeneralPurposeTest["DpBuf",		bufVectors];
GeneralPurposeTest["DpInv",		invVectors];
GeneralPurposeTest["DpOr",		orVectors];
GeneralPurposeTest["DpNor",		norVectors];
GeneralPurposeTest["DpAnd",		andVectors];
GeneralPurposeTest["DpNand",	nandVectors];
GeneralPurposeTest["DpXor",		xorVectors];
GeneralPurposeTest["DpXNor",		xnorVectors];


};

TestLatchOld: PROC = {
cell: 		CellType;
out0:		ROPE _ CoreName.RopeNm["out0"];
ctl1:		ROPE _ CoreName.RopeNm["1"];
XNode:	ROPE _ CoreName.RopeNm["XNode"];
rec: CoreClasses.RecordCellType;
latchVectors:	TestVectors _ NEW[TestVectorSeq[8]];
latchVectors[0]	_ [c1: H,		c0: H,		i0: L,		out: L];
latchVectors[1]	_ [c1: H,		c0: L,		i0: L,		out: L];
latchVectors[2]	_ [c1: H,		c0: L,		i0: H,		out: L];
latchVectors[3]	_ [c1: H,		c0: H,		i0: H,		out: H];
latchVectors[4]	_ [c1: H,		c0: L,		i0: H,		out: H];
latchVectors[5]	_ [c1: H,		c0: L,		i0: L,		out: H];
latchVectors[6]	_ [c1: H,		c0: H,		i0: L,		out: L];
latchVectors[7]	_ [c1: H,		c0: L,		i0: L,		out: L];
cell _ Extract["DpLatch"];
rec _ NARROW[cell.data];
FOR ii: INT IN [0..rec.size) DO
gate, ch1, ch2: ROPE;
IF rec[ii].type.class#CoreClasses.transistorCellClass THEN Signal[];
gate	_ CoreName.WireNm[rec[ii].actual[0]].n;
ch1	_ CoreName.WireNm[rec[ii].actual[1]].n;
ch2	_ CoreName.WireNm[rec[ii].actual[2]].n;
IF (gate=ctl1 OR gate=out0)	AND (ch1=XNode OR ch2=XNode) THEN {
transistorSizeRef: REF Ports.Drive _ NARROW
[CoreProperties.GetCellInstanceProp[from: rec[ii], prop: $RoseTransistorSize]];
IF transistorSizeRef=NIL THEN Signal[];
[ ] _ Rosemary.SetTransistorInstanceSize[rec[ii], driveWeak]};
ENDLOOP;
Simulate[cell, latchVectors]};

TestLatch: PROC = {
cell: 		CellType;
out0:		ROPE _ CoreName.RopeNm["out0"];
ctl1:		ROPE _ CoreName.RopeNm["1"];
XNode:	ROPE _ CoreName.RopeNm["XNode"];
latchVectors:	TestVectors _ NEW[TestVectorSeq[8]];
latchVectors[0]	_ [c1: H,		c0: H,		i0: L,		out: L];
latchVectors[1]	_ [c1: H,		c0: L,		i0: L,		out: L];
latchVectors[2]	_ [c1: H,		c0: L,		i0: H,		out: L];
latchVectors[3]	_ [c1: H,		c0: H,		i0: H,		out: H];
latchVectors[4]	_ [c1: H,		c0: L,		i0: H,		out: H];
latchVectors[5]	_ [c1: H,		c0: L,		i0: L,		out: H];
latchVectors[6]	_ [c1: H,		c0: H,		i0: L,		out: L];
latchVectors[7]	_ [c1: H,		c0: L,		i0: L,		out: L];
cell _ Extract["DpLatch"];
IFUSim.SetUp[cell];
Simulate[cell, latchVectors];
Simulate[cell, latchVectors, LIST["DpLatch", "DpLatchCtl"]]};

dpins: RECORD[
in, out, PhA, PhB, DShA, DShB, DShWt, DShRd, DShIn, DShOut, GND, VDD: INT _ -1];

DriverTest: RosemaryUser.TestProc = {
T: BOOL = TRUE; F: BOOL = FALSE;
vec: REF DrVecSeq _ NEW[DrVecSeq[9]];
DrVecSeq: TYPE = RECORD[SEQUENCE size: CARDINAL OF DrVec];
DrVec: TYPE = RECORD[
in, out, PhA, PhB, DShA, DShB, DShWt, DShRd, DShIn, DShOut: BOOL _ FALSE];
vec[0] _ [in:TRUE,	PhB:TRUE,	out:TRUE,		DShIn:F, DShA:T, DShB:T, DShOut:F];
vec[1] _ [in:TRUE,	PhB:TRUE,	out:TRUE,		DShIn:F, DShA:T, DShOut:F];
vec[2] _ [in:TRUE,	PhB:TRUE,	out:TRUE,		DShIn:F, DShA:F, DShOut:F];
vec[3] _ [in:TRUE,	PhB:TRUE,	out:TRUE,		DShIn:F, DShB:T, DShOut:F];
vec[4] _ [in:TRUE,	PhB:TRUE,	out:TRUE,		DShIn:F, DShB:F, DShOut:F];
vec[5] _ [in:TRUE,	PhB:TRUE,	out:TRUE];
vec[6] _ [in:TRUE,	PhB:F,		out:TRUE];
vec[7] _ [in:F,		PhB:F,		out:TRUE];
vec[8] _ [in:F,		PhB:TRUE,	out:F];
FOR index: CARDINAL IN [0..vec.size) DO
p[dpins.in].b			_ vec[index].in;
p[dpins.PhA].b		_ vec[index].PhA;
p[dpins.PhB].b		_ vec[index].PhB;
p[dpins.DShA].b		_ vec[index].DShA;
p[dpins.DShB].b		_ vec[index].DShB;
p[dpins.DShWt].b	_ vec[index].DShWt;
p[dpins.DShRd].b	_ vec[index].DShRd;
p[dpins.DShIn].b	_ vec[index].DShIn;
p[dpins.out].b		_ vec[index].out;
p[dpins.DShOut].b	_ vec[index].DShOut;
Eval[];
ENDLOOP };

DriverSimTestDo: PROC = {
testName: ROPE _ "DriverTest";
drive:			IFUCoreDrive.Drive;
driver:		CellType;
cell:			CellType;
tester:			RosemaryUser.Tester;
drive _ IFUCoreDrive.SpecificDrive[
dir:		in,
in:			"InAB",
out:		"OutBA",
inverted:	FALSE,
dual:		FALSE];
drive.inSh	_ "DShIn";
drive.outSh	_ "DShOut";
driver _ IFUCoreDrive.CellProc["DrTest", drive];
CoreFrame.Expand[hard, driver];
cell				_ CoreOps.Recast[CoreFrame.FCT[driver].cell];
IFUSim.SetUp[cell];
dpins.GND		_ CoreOps.GetWireIndex[cell.public, "GND"];
dpins.VDD		_ CoreOps.GetWireIndex[cell.public, "VDD"];
dpins.PhA		_ CoreOps.GetWireIndex[cell.public, "PhA"];
dpins.PhB		_ CoreOps.GetWireIndex[cell.public, "PhB"];
dpins.in			_ CoreOps.GetWireIndex[cell.public, "InAB"];
dpins.out			_ CoreOps.GetWireIndex[cell.public, "OutBA"];
dpins.DShA		_ CoreOps.GetWireIndex[cell.public, "DShA"];
dpins.DShB		_ CoreOps.GetWireIndex[cell.public, "DShB"];
dpins.DShWt		_ CoreOps.GetWireIndex[cell.public, "DShWt"];
dpins.DShRd		_ CoreOps.GetWireIndex[cell.public, "DShRd"];
dpins.DShIn		_ CoreOps.GetWireIndex[cell.public, "DShIn"];
dpins.DShOut	_ CoreOps.GetWireIndex[cell.public, "DShOut"];

[] _ Rosemary.SetFixedWire[ cell.public[dpins.GND],			L];
[] _ Rosemary.SetFixedWire[ cell.public[dpins.VDD],			H];
[] _ Ports.InitPort[wire: cell.public[dpins.PhA],					levelType: b, initDrive: none];
[] _ Ports.InitPort[wire: cell.public[dpins.PhB],					levelType: b, initDrive: none];
[] _ Ports.InitPort[wire: cell.public[dpins.in],					levelType: b, initDrive: none];
[] _ Ports.InitPort[wire: cell.public[dpins.out],					levelType: b, initDrive: force];
[] _ Ports.InitPort[wire: cell.public[dpins.DShA],				levelType: b, initDrive: none];
[] _ Ports.InitPort[wire: cell.public[dpins.DShB],				levelType: b, initDrive: none];
[] _ Ports.InitPort[wire: cell.public[dpins.DShWt],				levelType: b, initDrive: none];
[] _ Ports.InitPort[wire: cell.public[dpins.DShRd],				levelType: b, initDrive: none];
[] _ Ports.InitPort[wire: cell.public[dpins.DShIn],				levelType: b, initDrive: none];
[] _ Ports.InitPort[wire: cell.public[dpins.DShOut],				levelType: b, initDrive: force];

[] _ Ports.InitTesterDrive[wire: cell.public[dpins.PhA],			initDrive: force];
[] _ Ports.InitTesterDrive[wire: cell.public[dpins.PhB],			initDrive: force];
[] _ Ports.InitTesterDrive[wire: cell.public[dpins.in],			initDrive: force];
[] _ Ports.InitTesterDrive[wire: cell.public[dpins.out],			initDrive: expect];
[] _ Ports.InitTesterDrive[wire: cell.public[dpins.DShA],		initDrive: force];
[] _ Ports.InitTesterDrive[wire: cell.public[dpins.DShB],		initDrive: force];
[] _ Ports.InitTesterDrive[wire: cell.public[dpins.DShWt],		initDrive: force];
[] _ Ports.InitTesterDrive[wire: cell.public[dpins.DShRd],		initDrive: force];
[] _ Ports.InitTesterDrive[wire: cell.public[dpins.DShIn],		initDrive: force];
[] _ Ports.InitTesterDrive[wire: cell.public[dpins.DShOut],		initDrive: expect];

RosemaryUser.RegisterTestProc[testName, DriverTest];
tester _ RosemaryUser.TestProcedureViewer[
cellType: 		cell, 
testButtons:		LIST[testName], 
name:				testName, 
displayWires:	RosemaryUser.DisplayPortLeafWires[cell], 
cutSet:			CoreFlat.CreateCutSet[labels: LIST["DrLatch"]]]};


library: CoreLibrary.Library _ IFUCoreCells.library;

Library: PUBLIC PROC = {
DriverSimTestDo[];
TestAllSimples[];
TestLatchOld[];
TestLatch[];
TestSAdder[];
TestGPC[TRUE];
TestGPC[FALSE]};

END. 

®IFUTestLibrary.mesa 
Copyright c 1986 by Xerox Corporation.  All rights reserved.
Last Edited by Curry, September 30, 1986 10:39:00 am PDT
Don Curry October 30, 1986 9:38:01 pm PST

SoS.CheckDesignRules[
cell, library.design, NIL, TRUE,
$PWCoreLayout, $SinixCMosBInstance, $SinixCMosBWireGeometry];
IF CoreProperties.GetProp[cell.properties, SoS.DRVkey].value#NIL THEN Signal[];
example[0]		_ [c0: X,		c1: X,		i0: X,		i1: X,		out: X];
GeneralPurposeTest["DpPreChg",				bufVectors];
GeneralPurposeTest["DpInvDr",				bufVectors];
GeneralPurposeTest["DpTriDr",				bufVectors];
GeneralPurposeTest["DpSelect",				bufVectors];
GeneralPurposeTest["DpAdderGPC0",			bufVectors];
GeneralPurposeTest["DpAdderGPC1",			bufVectors];
GeneralPurposeTest["DpAdderSum",			bufVectors];
GeneralPurposeTest["DpAdderSerial",			bufVectors];
GeneralPurposeTest["DpStackBit",				bufVectors];
GeneralPurposeTest["DpStackBitSeparation",	bufVectors];
GeneralPurposeTest["DpFetchBufferBit",		bufVectors];

GeneralPurposeTest["DrInPosSing",			bufVectors];
GeneralPurposeTest["DrInNegSing",			bufVectors];
GeneralPurposeTest["DrInPosDual",			bufVectors];
GeneralPurposeTest["DrInNegDual",			bufVectors];

GeneralPurposeTest["DrLatch",				bufVectors];

GeneralPurposeTest["DrInA",					bufVectors];
GeneralPurposeTest["DrInB",					bufVectors];

GeneralPurposeTest["DrInInPos",				bufVectors];
GeneralPurposeTest["DrInInNeg",				bufVectors];

GeneralPurposeTest["DrOutPosSing",			bufVectors];
GeneralPurposeTest["DrOutNegSing",			bufVectors];
GeneralPurposeTest["DrOutPosDual",			bufVectors];
GeneralPurposeTest["DrOutNegDual",			bufVectors];

GeneralPurposeTest["DrOutAc",				bufVectors];
GeneralPurposeTest["DrOutBc",				bufVectors];
GeneralPurposeTest["DrOutPos",				bufVectors];
GeneralPurposeTest["DrOutNeg",				bufVectors];

GeneralPurposeTest["DrOutLatchA",			bufVectors];
GeneralPurposeTest["DrOutLatchB",			bufVectors];

GeneralPurposeTest["DrOutInPos",				bufVectors];
GeneralPurposeTest["DrOutInNeg",			bufVectors];
testerPort		_ Ports.CreatePort[cell, TRUE];
simulation	_ Rosemary.Instantiate[cell, testerPort];
display		_ RosemaryUser.DisplayViewer[
simulation,
cell,
"Driver Simulation Test",
RosemaryUser.DisplayPortLeafWires[cell]];
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