<> <> <> <> DIRECTORY CoreFlat, Ports, Rosemary; RoseTV: CEDAR DEFINITIONS = BEGIN <<>> <> <> <> Bool: TYPE = BOOL; Nat: TYPE = NAT; Cardinal: TYPE = CARDINAL; Int: TYPE = INT; -- [lsw, msw] LongCard: TYPE = LONG CARDINAL; -- [lsw, msw] Real: TYPE = REAL; -- [lsw, msw] ROPE: TYPE = Rosemary.ROPE; RTVal: TYPE = REF RTValRec; RTValRec: TYPE = RECORD[ path: ROPE _ NIL, field: ROPE _ NIL, ref: REF _ NIL, bad: BOOL _ FALSE, fldBitNm: FldBitNmProc _ NIL, buf: Ports.LevelSequence _ NIL, seq: SEQUENCE wwrSize: CARDINAL OF SignedFlatWire]; SignedFlatWire: TYPE = RECORD[ wire: CoreFlat.FlatWire _ NIL, inverted: BOOL _ FALSE ]; New: PROC[path, field: ROPE, ref: REF, struc: BOOL _ TRUE, fldBitNm: FldBitNmProc _ SimpleDotIndexing] RETURNS[rtv: RTVal]; <> <> < structured wire.>> NotImplemented: ERROR; XFer: PROC[sim: Rosemary.Simulation, rtv: RTVal] RETURNS[ref: REF]; <> <> XFerList: PROC[sim: Rosemary.Simulation, rtvs: LIST OF RTVal]; SimpleDotIndexing: FldBitNmProc; FldBitNmProc: TYPE = PROC[rtv: RTVal, index: INT] RETURNS[fieldBitNm: ROPE]; END.