IFUSimFetchBuf.mesa
Last edited by Curry October 21, 1986 7:02:13 pm PDT
Don Curry October 24, 1986 5:48:19 pm PDT
DIRECTORY Core, CoreFlat, CoreName, IFUSim, Rosemary, Ports, Rope;
IFUSimFetchBuf:
CEDAR
PROGRAM
IMPORTS CoreFlat, CoreName, IFUSim, Rosemary, Ports, Rope
EXPORTS IFUSim =
BEGIN
ROPE: TYPE = Core.ROPE;
CellType: TYPE = Core.CellType;
Signal: SIGNAL = CODE;
fetchBuf: ROPE ← Rosemary.Register[CoreName.RopeNm["FetchBuf"], FetchBufInit, FetchBufEval];
FetchBufWtWd: ROPE ← CoreName.RopeNm["FetchBufWtWd"];
FetchBufRdByte: ROPE ← CoreName.RopeNm["FetchBufRdByte"];
IPData: ROPE ← CoreName.RopeNm["IPData"];
Op: ROPE ← CoreName.RopeNm["Op"];
Alpha: ROPE ← CoreName.RopeNm["Alpha"];
Beta: ROPE ← CoreName.RopeNm["Beta"];
Gamma: ROPE ← CoreName.RopeNm["Gamma"];
Delta: ROPE ← CoreName.RopeNm["Delta"];
FetchBufState: TYPE = REF FetchBufStateRec;
FetchBufStateRec:
TYPE =
RECORD[
bytes: FetchBufBytes,
ipData: FetchWdPins,
op: FetchBytePins,
alpha: FetchBytePins,
beta: FetchBytePins,
gamma: FetchBytePins,
delta: FetchBytePins,
rdByte: FetchRowPins,
wtWd: FetchQRowPins ];
FetchBufBytes: TYPE = PACKED ARRAY [0..16) OF ARRAY [0..8) OF Ports.Level ← ALL[ALL[L]];
FetchWdPins: TYPE = ARRAY [0..32) OF CARDINAL;
FetchBytePins: TYPE = ARRAY [0..08) OF CARDINAL;
FetchRowPins: TYPE = ARRAY [0..16) OF CARDINAL;
FetchQRowPins: TYPE = ARRAY [0..04) OF CARDINAL;
FetchBufInitPort:
PUBLIC PROC [cell: CellType] = {
[]←Rosemary.BindCellType [cell, fetchBuf];
[]𡤌oreFlat.CellTypeCutLabels [cell, "UpOneLevel"];
FOR i:
INT
IN [0..cell.public.size)
DO
name: ROPE ← CoreName.WireNm[cell.public[i]].n;
sig: CoreName.SigRec ← CoreName.NameSig[name];
IF (cell.public[i].size#0) OR (name.Length[]=0) THEN Signal[];
SELECT sig.root
FROM
Op,
Alpha,
Beta,
Gamma,
Delta => []←Ports.InitPort[wire: cell.public[i], levelType: l, initDrive: drive];
IPData => []←Ports.InitPort[wire: cell.public[i], levelType: l, initDrive: none];
ENDCASE => []←Ports.InitPort[wire: cell.public[i], levelType: b, initDrive: none];
ENDLOOP};
FetchBufInit: Rosemary.InitProc = {
s: FetchBufState ←
IF oldStateAny #
NIL
THEN NARROW[oldStateAny]
ELSE NEW[FetchBufStateRec];
FOR bit:
INT
IN [0..cellType.public.size)
DO
name: ROPE ← CoreName.WireNm[cellType.public[bit]].n;
sig: CoreName.SigRec ← CoreName.NameSig[name];
SELECT sig.root
FROM
IPData => s.ipData [ IFUSim.Adj[sig.idx] ] ← bit; -- octal indexes
Op => s.op [ sig.idx ] ← bit;
Alpha => s.alpha [ sig.idx ] ← bit;
Beta => s.beta [ sig.idx ] ← bit;
Gamma => s.gamma [ sig.idx ] ← bit;
Delta => s.delta [ sig.idx ] ← bit;
FetchBufRdByte => s.rdByte [ sig.idx ] ← bit;
FetchBufWtWd => s.wtWd [ sig.idx ] ← bit;
ENDCASE ENDLOOP;
RETURN[s]};
FetchBufEval: Rosemary.EvalProc = {
PullDown:
PROC[byte: [0..16), bit: [0..8), old: Ports.Level]
RETURNS[Ports.Level] =
{RETURN[SELECT s.bytes[byte][bit] FROM L => L, X => X, ENDCASE => old]};
s: FetchBufState ← NARROW[stateAny];
lastRd: CARDINAL ← 0;
cntRd: CARDINAL ← 0;
FOR wd:
CARDINAL
IN [0..4)
DO
IF p[s.wtWd[wd]].b
THEN
FOR byte:
CARDINAL
IN [0..4)
DO
FOR bit: CARDINAL IN [0..8) DO
s.bytes[(wd*4+byte) MOD 16][bit] ← p[ s.ipData[byte*8+bit] ].l
ENDLOOP ENDLOOP ENDLOOP;
FOR row:
CARDINAL
IN [0..16)
DO
IF p[s.rdByte[row]].b THEN {cntRd ← cntRd + 1; lastRd ← row} ENDLOOP;
FOR bit:
CARDINAL
IN [0..8)
DO
p[s.op [bit] ].d ←
p[s.alpha [bit] ].d ←
p[s.beta [bit] ].d ←
p[s.gamma [bit] ].d ←
p[s.delta [bit] ].d ← (IF cntRd=0 THEN none ELSE drive);
SELECT cntRd
FROM
0 => {};
1 => {
p[s.op [bit] ].l ← PullDown[(lastRd+0) MOD 16, bit, p[s.op [bit] ].l];
p[s.alpha [bit] ].l ← PullDown[(lastRd+1) MOD 16, bit, p[s.alpha [bit] ].l];
p[s.beta [bit] ].l ← PullDown[(lastRd+2) MOD 16, bit, p[s.beta [bit] ].l];
p[s.gamma [bit] ].l ← PullDown[(lastRd+3) MOD 16, bit, p[s.gamma [bit] ].l];
p[s.delta [bit] ].l ← PullDown[(lastRd+4) MOD 16, bit, p[s.delta [bit] ].l]};
ENDCASE => {
p[s.op [bit] ].l ←
p[s.alpha [bit] ].l ←
p[s.beta [bit] ].l ←
p[s.gamma [bit] ].l ←
p[s.delta [bit] ].l ← X};
ENDLOOP};
END.