DIRECTORY CCDUtils, CD, Core, CoreClasses, CoreFrame, CoreGlue, CoreOps, CoreName, CoreWire, CoreXform, IFUCoreData, IO, Ports, PW, PWC, PWCore, Rosemary, RosemaryUser; IFUTests: CEDAR PROGRAM IMPORTS CCDUtils, CoreClasses, CoreFrame, CoreGlue, CoreOps, CoreName, CoreWire, CoreXform, IFUCoreData, IO, Ports, PW, PWC, Rosemary, RosemaryUser = BEGIN CellType: TYPE = Core.CellType; Wire: TYPE = Core.Wire; ROPE: TYPE = Core.ROPE; adder: Core.CellType; adderObj: CD.Object; decoObj: CD.Object; AdderTest: PROC[size: INT] = { xform: CoreXform.Xform _ CoreXform.GenXform[ LIST[ [size, 0] ] ]; sb: CellType = IFUCoreData.CellProc[ subClass: "SwitchBox", name: "SB", top: "( Ina. Inb. )", left: "( Junk )", right: "( Junk )", bot: "( Ina. Inb. )", xform: xform ]; adderMain: CellType = IFUCoreData.CellProc[ subClass: "Adder", name: "AdderMain", top: "( Ina. Inb. )", right: "( GND )", in: "( Ina. Inb. )", out: "( Out. )", bot: "( Out. )", xform: xform ]; adder _ CoreFrame.NewFrameCells[name: "Adder", rec: [first:top], cells:LIST[sb, adderMain]]; CoreFrame.Expand[hard, adder]; CoreFrame.NameFrame[adder]; [ ] _ CoreGlue.RouteHard[adder]; adderObj _ CCDUtils.Layout[ adder]; decoObj _ CCDUtils.OrnateFrame[ adder]; [ ] _ PW.Draw[decoObj]; TestAdder[size, CoreFrame.FCT[adder].cell]}; TestAdder: PROC[size: INT, cell: CellType] = { UpdateDisplay: PROC = { RosemaryUser.UpdateDisplay[display]}; DisplayAndSignal: PROC = { RosemaryUser.UpdateDisplay[display]; Signal[]}; twoToPwrSize: CARDINAL _ 1; ina: NAT = 0; inb: NAT = 1; out: NAT = 2; VDD: NAT = 3; GND: NAT = 4; junk: NAT = 5; pubSize: NAT = 6; testerWire: CoreWire.CWire; testerPort: Ports.Port; display: RosemaryUser.RoseDisplay; simulation: Rosemary.Simulation; newCell: CellType; public: Wire _ CoreOps.CreateWires[pubSize]; public[ina] _ CoreOps.CreateWires[size, "Ina"]; public[inb] _ CoreOps.CreateWires[size, "Inb"]; public[out] _ CoreOps.CreateWires[size, "Out"]; public[VDD] _ CoreOps.CreateWires[0, "VDD"]; public[GND] _ CoreOps.CreateWires[0, "GND"]; public[junk] _ CoreOps.CreateWires[0, "Junk"]; FOR bit: INT IN [0..size) DO public[ina][bit] _ CoreOps.CreateWires[0, IO.PutFR["Ina.%g", IO.int[bit]]]; public[inb][bit] _ CoreOps.CreateWires[0, IO.PutFR["Inb.%g", IO.int[bit]]]; public[out][bit] _ CoreOps.CreateWires[0, IO.PutFR["Out.%g", IO.int[bit]]]; ENDLOOP; newCell _ RestructuredCell[public, cell]; PWC.SetAbutX[newCell]; [] _ PWC.Layout[newCell]; testerWire _ [newCell.public]; []_Ports.InitPort[wire: testerWire.i[ina].w, levelType: c]; []_Ports.InitPort[wire: testerWire.i[inb].w, levelType: c]; []_Ports.InitPort[wire: testerWire.i[out].w, levelType: c]; []_Ports.InitTesterDrive[wire: testerWire.i[ina].w, initDrive: force]; []_Ports.InitTesterDrive[wire: testerWire.i[inb].w, initDrive: force]; []_Ports.InitTesterDrive[wire: testerWire.i[out].w, initDrive: none]; FOR bit: INT IN [0..size) DO twoToPwrSize _ twoToPwrSize*2 ENDLOOP; [ ] _ Rosemary.SetFixedWire[testerWire.w[VDD], H]; [ ] _ Rosemary.SetFixedWire[testerWire.w[GND], L]; [ ] _ Rosemary.SetFixedWire[testerWire.w[junk], L]; testerPort _ Ports.CreatePort[testerWire.w, TRUE]; simulation _ Rosemary.InstantiateInstances[newCell, testerPort]; display _ RosemaryUser.DisplayViewer[simulation, newCell, "IFU Test", RosemaryUser.DisplayCellTypePortLeafWires[newCell]]; FOR arga: CARDINAL IN [0..twoToPwrSize) DO FOR argb: CARDINAL IN [0..twoToPwrSize) DO -- check for hidden state testerPort[ina].c _ arga; testerPort[inb].c _ argb; Rosemary.Settle[simulation]; UpdateDisplay[]; IF (testerPort[out].c#((arga+argb) MOD twoToPwrSize)) THEN DisplayAndSignal[]; ENDLOOP; ENDLOOP }; Signal: SIGNAL = CODE; RestructuredCell: PROC[public: Wire, cell: CellType] RETURNS[new: CellType]= { data: CoreClasses.RecordCellType _ NEW[CoreClasses.RecordCellTypeRec[1]]; context: CoreName.Context _ CoreName.NewContext[]; actual: Core.Wire _ CoreOps.CreateWires[cell.public.size]; count: NAT _ 0; addToCtx: PROC[wire: Wire] = {IF NOT CoreName.CtxRegisterWire[context, wire] THEN Signal[]; count _ count+1}; [ ] _ CoreOps.VisitAtomicWires[public, addToCtx]; IF count#cell.public.size THEN Signal[]; -- new public has extras FOR i: INT IN [0..cell.public.size) DO name: ROPE _ CoreName.WireNm[cell.public[i]].n; actual[i] _ CoreName.CtxNameToWire[context, name]; IF actual[i]=NIL THEN Signal[]; -- incomplete new public ENDLOOP; data.internal _ public; data[0] _ NEW[CoreClasses.CellInstanceRec _ [actual, cell]]; new _ NEW[Core.CellTypeRec _ [ class: CoreClasses.recordCellClass, public: public, data: data ]]}; END. ÊIFUTests.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Curry, August 13, 1986 6:59:12 am PDT [ ] _ PW.Draw[ adderObj]; Uses short wire names to generate corresponding actual ÊÌ˜šœ™Icodešœ<™