FetchBufMain:
PROC [name:
ROPE]
RETURNS[cellType: Core.CellType] = {
BlockRightSignals: CoreOps.EachWireProc = {
side: CoreBlock.Sides ← CoreBlock.GetWireSide[wire];
SELECT CoreName.WireNm[wire].n
FROM
VDD, GND => RETURN;
ENDCASE => [ ] ← CoreBlock.DelWireSide[wire, right]};
Rename: CoreInstCell.RenameProc =
{RETURN[TranslateGenericSignal[old, wd, byte, bit]]};
wd, byte, bit: INT ← 0; -- must be here for Rename
library: CoreLibrary.Library ← IFUCoreCells.library;
frame, top, mid, bot, wdFrame, rowFrame: CoreFrame.Frame;
temp: Core.CellType;
genTop: Core.CellType ← CoreLibrary.Get[library, "DpFetchBufNyblTop"];
genMidBody: Core.CellType ← CoreLibrary.Get[library, "DpFetchPDBufferBitBody"];
genBot: Core.CellType ← CoreLibrary.Get[library, "DpFetchBufNyblBot"];
cellType ← CoreFrame.NewFrameCell[3, name, [first: top]];
frame ← CoreFrame.FCT[cellType];
frame.seq[0] ← CoreFrame.NewFrameCell[8, "Top", [first: left]];
frame.seq[1] ← CoreFrame.NewFrameCell[4, "Heart", [first: bottom]];
frame.seq[2] ← CoreFrame.NewFrameCell[8, "Bot", [first: left]];
top ← CoreFrame.FCT[frame.seq[0]];
mid ← CoreFrame.FCT[frame.seq[1]];
bot ← CoreFrame.FCT[frame.seq[2]];
FOR bit
DECREASING
IN [0..8)
DO
temp ← CoreInstCell.SpecificGeneric[genTop, Rename];
top.seq[bit] ← CoreFrame.NewFrameCell[0, NIL, [first: left, cell: temp]];
temp ← CoreInstCell.SpecificGeneric[genBot, Rename];
bot.seq[bit] ← CoreFrame.NewFrameCell[0, NIL, [first: left, cell: temp]];
ENDLOOP;
FOR wd
DECREASING
IN [0..4)
DO
wdR: ROPE ← IO.PutFR["WtWd%g", IO.int[wd]];
mid.seq[wd] ← CoreFrame.NewFrameCell[4, NIL, [first: bottom]];
wdFrame ← CoreFrame.FCT[mid.seq[wd]];
FOR byte
DECREASING
IN [0..4)
DO
byteR: ROPE ← IO.PutFR["WtByte%g", IO.int[byte]];
genMidX: Core.CellType ← CoreLibrary.Get
[library, "DpFetchPDBufferBitX", FALSE, LIST[wdR, byteR]];
wdFrame.seq[byte] ← CoreFrame.NewFrameCell[16, "Byte", [first: left]];
rowFrame ← CoreFrame.FCT[wdFrame.seq[byte]];
FOR bit
DECREASING
IN [0..8)
DO
temp ← CoreInstCell.SpecificGeneric[genMidX, Rename];
rowFrame.seq[2*bit+0] ← CoreFrame.NewFrameCell[0,NIL,[first: left, cell: temp]];
temp ← CoreInstCell.SpecificGeneric[genMidBody, Rename];
rowFrame.seq[2*bit+1] ← CoreFrame.NewFrameCell[0,NIL,[first: left, cell: temp]];
ENDLOOP;
ENDLOOP;
ENDLOOP;
top.cell ← CoreFrame.RecastFrameHard[frame.seq[0]];
mid.cell ← CoreFrame.RecastFrameHard[frame.seq[1]];
bot.cell ← CoreFrame.RecastFrameHard[frame.seq[2]];
top.seq ← NEW[CoreFrame.FrameSeq[0]];
mid.seq ← NEW[CoreFrame.FrameSeq[0]];
bot.seq ← NEW[CoreFrame.FrameSeq[0]];
[ ] ← CoreOps.VisitWire[mid.cell.public, BlockRightSignals];
[ ] ← CoreOps.VisitWire[bot.cell.public, BlockRightSignals];
};
TranslateGenericSignal:
PROC[aName:
ROPE, wd, byte, bit:
INT]
RETURNS[ROPE]= {
sig: Sig;
index: INT ← -1;
row: INT ← wd*4+byte;
iChar: CHAR ← Rope.Fetch[aName, aName.Length[]-1];
rowBit: ROPE;
indexBit: ROPE;
rowIndexBit: ROPE;
IF iChar
IN ['0..'4]
THEN
{index ← iChar-'0; aName ← Rope.Substr[aName, 0, aName.Length[]-1]};
sig ← NARROW[HashTable.Fetch[xlateTable, aName].value];
IF sig = NIL THEN Signal[];
SELECT sig^
FROM
cycle, dn, wt, pass, in, out => IF index=-1 THEN Signal[];
ENDCASE;
rowBit ← IO.PutFR["[%g][%g]", IO.int[ row], IO.int[bit]];
indexBit ← IO.PutFR["[%g][%g]", IO.int[ index ], IO.int[bit]];
rowIndexBit ← IO.PutFR["[%g][%g]", IO.int[( row+ index) MOD 16 ], IO.int[bit]];
SELECT sig^
FROM
cycle => RETURN[IO.PutFR["FetchBufCycle%g", IO.rope[indexBit] ] ];
dn => RETURN[IO.PutFR["FetchBufCycle%g", IO.rope[rowIndexBit] ] ];
rd => RETURN[IO.PutFR["FetchBufRdByteAc.%g", IO.int[row]]];
wt => RETURN[IO.PutFR["FetchBufWtWdBc.%g", IO.int[index]]];
pass => RETURN[IO.PutFR["PCBus.%02b", IO.int[index*8+bit]]];
in => RETURN[IO.PutFR["IPData.%02b", IO.int[index*8+bit]]];
out => RETURN[IO.PutFR["%g%g", IO.rope[outs[index]], IO.int[bit]]];
next => RETURN[IO.PutFR["FetchBufNext.%g", IO.rope[rowBit]]];
last => RETURN[IO.PutFR["FetchBufLast.%g", IO.rope[rowBit]]];
vdd => RETURN[aName];
gnd => RETURN[aName];
ENDCASE => ERROR};
outs:
ARRAY[0..4]
OF
ROPE =
["AlphaA.", "BetaA.", "GammaA.", "DeltaA.", "OpA."];
Sig: TYPE = REF SigType;
SigType: TYPE = {cycle, dn, rd, wt, pass, in, next, last, out, gnd, vdd};
xlateTable: HashTable.Table;
InitXlateTable:
PROC = {
Store:
PROC[refName:
ROPE, sigType: SigType] = {
refName ← CoreName.RopeNm[refName];
[] ← HashTable.Store[xlateTable, refName, NEW[SigType ← sigType]]};
xlateTable ← HashTable.Create[equal: HashTable.RopeEqual, hash: HashTable.HashRope];
Store[ "busCycle", cycle];
Store[ "dn", dn];
Store[ "rd", rd];
Store[ "wt", wt];
Store[ "pass", pass];
Store[ "in", in];
Store[ "next", next];
Store[ "last", last];
Store[ "out", out];
Store[ "GND", gnd];
Store[ "VDD", vdd] };
InitXlateTable[];