<> <> <> <> <<>> DIRECTORY Core, CoreFrame, CoreGlue, CoreName, CoreOps, CoreProperties, IFUCoreCtl, IFUCoreDrive, IO, Lists, PLAOps, REFBit, Rope; IFUCoreCtlImpl: CEDAR PROGRAM IMPORTS CoreFrame, CoreGlue, CoreName, CoreOps, CoreProperties, IFUCoreCtl, IFUCoreDrive, IO, Lists, PLAOps, REFBit, Rope EXPORTS IFUCoreCtl = BEGIN ROPE: TYPE = Core.ROPE; CellType: TYPE = Core.CellType; Wire: TYPE = Core.Wire; SigRec: TYPE = CoreName.SigRec; Section: TYPE = IFUCoreCtl.Section; PLASection: TYPE = IFUCoreCtl.PLASection; PLASectionRec: TYPE = IFUCoreCtl.PLASectionRec; PLADescription: TYPE = IFUCoreCtl.PLADescription; XsFormSeqRec: TYPE = IFUCoreCtl.XsFormSeqRec; PublicRefRec: TYPE = IFUCoreCtl.PublicRefRec; XlatePubSeqRec: TYPE = IFUCoreCtl.XlatePubSeqRec; PLAType: TYPE = IFUCoreDrive.PLAType; Drive: TYPE = IFUCoreDrive.Drive; DriveRec: TYPE = IFUCoreDrive.DriveRec; RowType: TYPE = IFUCoreDrive.RowType; Dir: TYPE = IFUCoreDrive.Dir; DrGate: TYPE = IFUCoreDrive.DrGate; Ph: TYPE = IFUCoreDrive.Ph; Polarity: TYPE = IFUCoreDrive.Polarity; Signal: SIGNAL = CODE; ctlCellClass: PUBLIC Core.CellClass _ CoreOps.SetClassPrintProc[ NEW[Core.CellClassRec _ [name: "IFUCoreCtl", recast: NIL]], ClassPrintProc]; ClassPrintProc: CoreOps.PrintClassProc = { ref: PLASection _ NARROW[data]; out.PutF["\nControl: ", IO.rope[ ref.desc.name ] ] }; CellProc: PUBLIC PROC [ section: Section, desc: PLADescription ] RETURNS [cellType: Core.CellType] = { -- ctlCellClass SELECT section FROM complete => { name: ROPE _ desc.name.Cat["Cmpl"]; cellType _ CoreFrame.NewFrameCells[name: name, rec: [first: top], cells: LIST[ CellProc[outSec, desc ], CellProc[inSec, desc ] ] ] }; outSec => { name: ROPE _ desc.name.Cat["OutSec"]; cellType _ CoreFrame.NewFrameCells[name: name, rec: [first: left], cells: LIST[ CellProc[outBody, desc ], CellProc[outDr, desc ] ] ] }; inSec => { name: ROPE _ desc.name.Cat["InSec"]; desc.includeIns _ TRUE; cellType _ CoreFrame.NewFrameCells[name: name, rec: [first: left], cells: LIST[ CellProc[inSB, desc ], CellProc[inDr, desc ] ] ] }; ENDCASE => { name: ROPE _ SELECT section FROM outBody => desc.name.Cat["OutBody"], outDr => desc.name.Cat["OutDr"], inSB => desc.name.Cat["InSB"], inDr => desc.name.Cat["InDr"], ENDCASE => ERROR; cellType _ CoreOps.SetCellTypeName[ NEW [ Core.CellTypeRec _ [ class: ctlCellClass, public: CoreOps.CreateWires[0], data: NEW[PLASectionRec _ [desc: desc, section: section] ] ] ], name]; CoreFrame.SetFrameExpandProc[soft, cellType, NEW[CoreFrame.ExpandProc_ Expand]]; CoreFrame.SetFrameExpandProc[hard, cellType,NEW[CoreFrame.ExpandProc_Expand]]}}; Expand: CoreFrame.ExpandProc = { secRec: PLASection _ NARROW[frameCT.data]; MakePLA[secRec.desc]; SELECT secRec.section FROM inDr => {CoreFrame.Expand[hard, secRec.desc.inDrCT]; frameCT^ _ secRec.desc.inDrCT^}; outDr => {CoreFrame.Expand[hard, secRec.desc.outDrCT]; frameCT^ _ secRec.desc.outDrCT^}; inSB => {CoreFrame.Expand[hard, secRec.desc.inSBCT]; frameCT^ _ secRec.desc.inSBCT^}; outBody => { frameCT^ _ secRec.desc.outBodyCT^}; ENDCASE => Signal[]; CoreFrame.SetFrameExpandProc[soft, frameCT, NIL]; CoreFrame.SetFrameExpandProc[hard, frameCT, NIL] }; MakePLA: PUBLIC PROC [desc: PLADescription] = { MakePLA1[desc]; MakePLA2[desc]}; MakePLA1: PUBLIC PROC [desc: PLADescription] = { OPEN desc; bitForm: REFBit.Format; IF valid THEN RETURN; IF plaType=precharged AND termsPerHeader=1000 THEN termsPerHeader_20; IF ttt=NIL THEN ttt _ PLAOps.ReadPLAFile[name.Cat[".ttt"], log]; bitForm _ REFBit.Desc[ttt.data].bitForm; FOR bit: INT DECREASING IN [0..bitForm.size) DO bitForm[bit].name _ CoreName.BitRopeToSigRope[bitForm[bit].name]; bitForm[bit].nameInv _ CoreName.BitRopeToSigRope[bitForm[bit].nameInv]; ENDLOOP; bitForm _ REFBit.Desc[ttt.out].bitForm; FOR bit: INT DECREASING IN [0..bitForm.size) DO bitForm[bit].name _ CoreName.BitRopeToSigRope[bitForm[bit].name]; bitForm[bit].nameInv _ CoreName.BitRopeToSigRope[bitForm[bit].nameInv]; ENDLOOP; IF inDrs=NIL THEN { initial: IFUCoreDrive.DriveRec _ [ drDir: in, dualOut: TRUE, in: [pos, plaPhs[drIn] ], ref: [pos, plaPhs[drInClk] ], out: [pos, plaPhs[plaIn] ] ]; inDrs _ IFUCoreDrive.RefToDrives[ttt.data, initial]}; IF outDrs=NIL THEN { initial: IFUCoreDrive.DriveRec _ [ drDir: out, in: [ pol: SELECT desc.plaType FROM precharged, hot=>neg ENDCASE=>pos, ph: plaPhs[drOutClk] ], ref: [pos, plaPhs[drOutClk] ], out: [pos, plaPhs[drOut] ], plaType: desc.plaType, fire: desc.fire, fireV: desc.fireV, nPreChg: desc.nPreChg ]; outDrs _ IFUCoreDrive.RefToDrives[ttt.out, initial]} }; <<>> <> <> <> <> <> <> <<[[TRUE, inForm[i].name, inForm[i].nameInv, plaPhs[plaIn]]], plaInNames];>> <> <<[FALSE, inForm[i].name, inForm[i].nameInv, plaPhs[plaIn]], plaInNames];>> <> <> <> <> <> <<[FALSE, outForm[i].name, outForm[i].nameInv, plaPhs[drOut]], plaOutNames];>> <> <> <> <> <> <<[FALSE, outForm[i].name, outForm[i].nameInv, plaPhs[drOut]], drSignalOrder];>> <> MakePLA2: PUBLIC PROC [desc: PLADescription] = { OPEN desc; IF valid THEN RETURN; IF plaInNames=NIL THEN { FOR list: IFUCoreDrive.Drives _ inDrs, list.rest WHILE list#NIL DO IF list.first.drRowType#conn THEN LOOP; plaInNames _ CONS[IFUCoreDrive.DriveName[list.first, out], plaInNames]; plaInNames _ CONS[IFUCoreDrive.DriveName[list.first, nout], plaInNames] ENDLOOP; plaInNames _ Lists.ReverseList[plaInNames]}; IF plaOutNames=NIL THEN { FOR list: IFUCoreDrive.Drives _ outDrs, list.rest WHILE list#NIL DO IF list.first.drRowType#conn THEN LOOP; plaOutNames _ CONS[IFUCoreDrive.DriveName[list.first, in], plaOutNames] ENDLOOP; plaOutNames _ Lists.ReverseList[plaOutNames]}; IF drSignalOrder=NIL THEN { FOR list: IFUCoreDrive.Drives _ outDrs, list.rest WHILE list#NIL DO IF list.first.drRowType#conn THEN LOOP; drSignalOrder _ CONS[IFUCoreDrive.DriveName[list.first, in], drSignalOrder] ENDLOOP; drSignalOrder _ Lists.ReverseList[drSignalOrder]}; BuildConnTranslationArray[desc]; SELECT plaType FROM hot => IFUCoreCtl.MakeHotPLA[desc]; precharged => IFUCoreCtl.MakePreChargedPLA[desc]; ENDCASE => ERROR; < IFUCoreCtl.MakeStaticPLA[desc];>> outSh _ inSh; IF includeIns THEN outSh _ IFUCoreDrive.ConnectDrives[inDrs, outSh]; outSh _ IFUCoreDrive.ConnectDrives[outDrs, outSh]; IF desc.inSBCT =NIL THEN desc.inSBCT _ CoreGlue.CellProc[t: conn, r: conn]; IF desc.inDrCT =NIL THEN desc.inDrCT _ IFUCoreDrive.DrivesToFrame[desc.name.Cat["InDr"], desc.inDrs]; IF desc.outDrCT =NIL THEN desc.outDrCT _ IFUCoreDrive.DrivesToFrame[desc.name.Cat["OutDr"], desc.outDrs]; <> valid _ TRUE}; ifuCoreCtlPLADesc: ATOM = CoreProperties.RegisterProperty[prop: $IFUCoreCtlPLADesc]; gnd: NAT _ 0; GND: ROPE _ CoreName.RopeNm["GND"]; vdd: NAT _ 1; VDD: ROPE _ CoreName.RopeNm["VDD"]; in: NAT _ 2; out: NAT _ 3; <> <> <> <> <> <<[name, nameInv, dual, inverted, cy, idx] _ CoreName.NormalFormatNames[format[bit]];>> <<>> <> <<>> <> <neg, neg=>pos, ENDCASE=>ERROR;>> <<[inv, name] _ CoreName.SelectName[(relSig.pol=neg)#inv, drive.name, drive.nameInv];>> <> <> <<[not, format[bit].name, format[bit].nameInv, ph]] };>> <> <> <> <> <> <> <> <> <> <> <> <> <> <<[ ] _ HashTable.Store[table, name, NEW[PublicRefRec _ [in, FALSE, bit]]];>> <<[ ] _ HashTable.Store[table, nameInv, NEW[PublicRefRec _ [in, TRUE, bit]]];>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> < {ref_NIL; gnd _ pub; LOOP};>> < {ref_NIL; vdd _ pub; LOOP};>> < {>> <> <> <> <> <<[] _ Ports.InitPort[wire: recCell.public[gnd]];>> <<[] _ Ports.InitPort[wire: recCell.public[vdd]];>> <<[] _ Rosemary.SetFixedWire[recCell.public[vdd], H];>> <<[] _ Rosemary.SetFixedWire[recCell.public[gnd], L];>> <> <> <> <> <> <<[] _ Rosemary.BindCellType[>> <> <> <> <> <> <> <<[] _ Rosemary.AddCutSets[cellType: recCell, cs1: "JustAboveTransistors"]};>> <> <<{RETURN[CoreProperties.GetCellTypeProp[from: cellType, prop: ifuCoreCtlPLADesc]]};>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<>> <> <> <> <> <> <> <> <<>> <<[] _ Ports.InitPort[wire: recCell.public[gnd], initType: l];>> <<[] _ Ports.InitPort[wire: recCell.public[vdd], initType: l];>> <<[] _ Ports.InitPort[wire: recCell.public[in], initType: composite];>> <<[] _ Ports.InitPort[wire: recCell.public[out], initType: composite, initDrive: drive];>> <> <<[] _ Ports.InitPort[wire: recCell.public[in][bit], initType: l] ENDLOOP;>> <> <<[] _ Ports.InitPort[wire: recCell.public[out][bit], initType: l, initDrive: drive] ENDLOOP;>> <<>> <<[] _ Rosemary.BindCellType[>> <> <> <> <> <> <> <<[] _ Rosemary.AddCutSets[cellType: recCell, cs1: "JustAboveTransistors"]};>> BuildConnTranslationArray: PROC [desc: PLADescription ] = { index: INT _ -1; smlOutNames: LIST OF ROPE; log.PutRope["\n Building pla translation array"]; <> desc.connSeq _ NEW[IFUCoreCtl.ConnSeq[Lists.ListLength[desc.drSignalOrder]]]; FOR list: LIST OF ROPE _ desc.drSignalOrder, list.rest WHILE list#NIL DO pos: INT _ Lists.ListItemIndex[desc.plaInNames, list.first]; index _ index+1; IF pos#-1 THEN { desc.connSeq[index] _ [index: pos/2, isOutput: FALSE, isLeftSide: (pos MOD 2 = 0)]; LOOP}; pos _ Lists.ListItemIndex[desc.plaOutNames, list.first]; IF pos=-1 THEN ERROR; -- Signal name not found; smlOutNames _ CONS[list.first, smlOutNames]; desc.connSeq[index] _ [index: pos, isOutput: TRUE, isLeftSide: FALSE]; ENDLOOP; smlOutNames _ Lists.ReverseList[smlOutNames]; desc.smlToBigOut _ NEW[IFUCoreCtl.XsFormSeqRec[Lists.ListLength[smlOutNames]]]; FOR i: CARDINAL IN [0..desc.smlToBigOut.size) DO desc.smlToBigOut[i] _ Lists.ListItemIndex[desc.plaOutNames, Lists.ListIndexItem[smlOutNames, i]] ENDLOOP; desc.plaOutNames _ smlOutNames; FOR index: INT IN [0..desc.connSeq.size) DO desc.connSeq[index].dr _ desc.outDrs.first; desc.outDrs _ desc.outDrs.rest ENDLOOP; IF desc.outDrs#NIL THEN Signal}; log: IO.STREAM _ CoreFrame.GetLog[]; END. <<>>