IFetcherTest.rose
Last edited by: McCreight, February 22, 1984 3:55 pm
Directory Dragon, DragOpsCross;
Imports BitOps, RoseRun, RoseTesting;
Library Cache, IFetcher;
SimpleIDecoder: CELL [
Timing and housekeeping interface
PhA, PhB<BOOL,
Reset<BOOL,
Vdd, Gnd<BOOL,
PadVdd, PadGnd<BOOL,
Interface within IFU
InstReadyA<BOOL, -- generated during PhA
PreOpA, PreAlphaA, PreBetaA, PreGammaA, PreDeltaA<INT[8], -- generated during PhA
PreLengthA<INT[3], -- generated during PhA
GetNextInstB, JumpB>BOOL, -- used during PhB
JumpTargetB>INT[32], -- used during PhB
PreFetchFaultedB<BOOL, -- generated during PhB (there's no hurry)
Serial debugging interface
DShift<BOOL,
DExecute<BOOL,
DNSelect<BOOL,
DHold<BOOL,
DDataIn<BOOL,
DDataOut=BOOL
]
State
npcA, npcB: Dragon.Word,
opA, alphaA, betaA, gammaA, deltaA: Dragon.Byte,
iLengthA: [0..5],
holdA, resetA, instReadyA, preFetchFaultedA, preFetchFaultedB: BOOL
EvalSimple
IF PhA THEN
BEGIN
holdA ← DHold;
IF NOT DHold THEN
BEGIN
resetA ← Reset;
instReadyA ← InstReadyA;
opA ← PreOpA;
alphaA ← PreAlphaA;
betaA ← PreBetaA;
gammaA ← PreGammaA;
deltaA ← PreDeltaA;
iLengthA ← PreLengthA;
preFetchFaultedA ← preFetchFaultedB;
npcA ← npcB;
END;
END;
IF PhB THEN
BEGIN
IF NOT holdA THEN
BEGIN
preFetchFaultedB ← PreFetchFaultedB;
SELECT TRUE FROM
resetA =>
BEGIN
GetNextInstB ← FALSE;
JumpB ← TRUE;
npcB ← 64 -- fake --;
END;
InstReadyA =>
BEGIN OPEN DragOpsCross;
SELECT TRUE FROM
opA = dJB, (opA IN [dRJBformat..eRJBformat]) AND ((opA-dRJBformat) MOD 2) = 1 =>
BEGIN
GetNextInstB ← FALSE;
JumpB ← TRUE;
npcB ← npcA+alphaA-(IF alphaA < 128 THEN 0 ELSE 256);
END;
opA = dJDB =>
BEGIN
GetNextInstB ← FALSE;
JumpB ← TRUE;
npcB ← npcA+256*Dragon.Word[betaA]+alphaA-Dragon.Word[IF betaA < 128 THEN 0 ELSE 65536];
END;
opA = dDFC =>
BEGIN
GetNextInstB ← FALSE;
JumpB ← TRUE;
npcB ← 256*(256*(256*Dragon.Word[deltaA]+gammaA)+betaA)+alphaA;
END;
ENDCASE =>
BEGIN
GetNextInstB ← TRUE;
JumpB ← FALSE;
npcB ← npcA+iLengthA;
END;
END;
preFetchFaultedA =>
BEGIN
GetNextInstB ← FALSE;
JumpB ← TRUE;
npcB ← 128 -- fake --;
END;
ENDCASE -- instruction not ready yet -- =>
BEGIN
GetNextInstB ← JumpB ← FALSE;
npcB ← npcA;
END;
JumpTargetB ← BitOps.ILID[source: npcB, container: JumpTargetB, containerWidth: 32, fieldPosition: 0, fieldWidth: 32];
END;
END;
ENDCELL;
IFetcherTest: CELL [
Timing and housekeeping interface
PhA, PhB<BOOL,
Reset<BOOL,
Vdd, Gnd<BOOL,
PadVdd, PadGnd<BOOL,
Serial debugging interface
DShift<BOOL,
DExecute<BOOL,
DNSelect<BOOL,
DHold<BOOL,
DDataIn<BOOL,
DDataOut=BOOL
]
Expand
P Interfaces for instruction cache
IPData: INT[32]; -- address to cache during PhA, data to/from cache during PhB
IPCmd: Mnemonic["PBusCommands"]; -- during PhA
IPReject: BOOL; -- during PhB
IPFault: BOOL; -- during PhB
IPPageFault: BOOL; -- during PhB
IPParity: BOOL; -- during PhB
IPNPError: BOOL;
Interface within IFU
InstReadyA: BOOL; -- generated during PhA
PreOpA, PreAlphaA, PreBetaA, PreGammaA, PreDeltaA: INT[8]; -- generated during PhA
PreLengthA: INT[3]; -- generated during PhA
GetNextInstB, JumpB: BOOL; -- used during PhB
JumpTargetB: INT[32]; -- used during PhB
PreFetchFaultedB: BOOL; -- generated during PhB (there's no hurry)
Main memory interface .. not used
MData: INT[32];
MCmd: Mnemonic["MBusCommands"];
MNShared: BOOL;
MParity: BOOL;
MNError: BOOL;
MReady: BOOL;
MRq: BOOL;
MNewRq: BOOL;
MGnt: BOOL;
fetcher: IFetcher[];
cache: Cache[PData: IPData, PCmd: IPCmd, PReject: IPReject, PFault: IPFault, PPageFault: IPPageFault, PParity: IPParity, PNPError: IPNPError];
decoder: SimpleIDecoder[]
BlackBoxTest
realHandle: REF RoseTesting.CellTestHandleRep;
oldIO, newIO: IFetcherTestIORef;
TRUSTED {realHandle ← LOOPHOLE[handle]};
oldIO ← NARROW[realHandle.tester.realCellStuff.oldIO];
newIO ← NARROW[realHandle.tester.realCellStuff.newIO];
instructions^ ← newIO^;
IF oldIO^ = newIO^ AND (PhA OR PhB) THEN
BEGIN -- user did nothing, so we push the simulation along ourselves
wasPhA: BOOL = PhA;
PhA ← PhB ← FALSE;
[] ← RoseRun.Eval[handle];
PhB ← wasPhA;
PhA ← NOT wasPhA;
[] ← RoseRun.Eval[handle];
END;
[] ← RoseRun.Eval[handle];
[] ← RoseRun.Eval[handle]
ENDCELL