
<<DragonMicrocode.mesa>>
<<Copyright © 1984 by Xerox Corporation.  All rights reserved.>>
<<Last edited by McCreight, March 27, 1984 10:07:48 am PST>>
<<Last edited by Curry, July 31, 1984 11:33:49 am PDT>>

DIRECTORY
Dragon;

DragonMicrocode: CEDAR DEFINITIONS =
BEGIN

Exceptions:        TYPE = MACHINE DEPENDENT {
none,            reserve1,        aboutToReset,    reset,        
epFault,        euCC,            epReject,            cJump,
rschlWait,    iStkOFlow,    eStkOFlow,        iFtchFault,
reserve12,    reserve13,    reserve14,        reserve15};
CondEffect:        TYPE = MACHINE DEPENDENT {macroTrap, macroJump, microJump};
IStackPostEffect:    TYPE = MACHINE DEPENDENT {none, push, pop};
ITrapPostEffect:    TYPE = MACHINE DEPENDENT {none, enable, disable};
XBSource:        TYPE = MACHINE DEPENDENT {
pcPlusLen,            pcPlusXA,            pcPlusAlphaS,        pcPlusBetaAlphaS,
pc,                    xA,                    reserve6,                deltaGammaBetaAlpha,
xopGenerator,        trapPCGenerator,    reserve10,            reserve11,
iStackPC,                pipe3PC,                reserve14,            reserve15};

PipedPLSASpec:    TYPE = MACHINE DEPENDENT {pls, pLenLSnext, pAlphasLSnext};
XASource:        TYPE = MACHINE DEPENDENT {
none,            bAddrIFUReg,    reserve2,        reserve3, -- Both essentially none
alpha,            beta,                betaAlpha,    deltaGammaBetaAlpha,
fpLdAMsw,    fpLdALsw,        fpUnldMsw,    fpUnldLsw,
fpLdBMsw,    fpLdBLsw,        reserve14,    fpLdMode};

Reg:                TYPE = RECORD [ s0: RegSum0, s1: RegSum1 ]; -- 7 bits
RegSum0:            TYPE = MACHINE DEPENDENT {cBase, aBase, iRef, xBus, s, l, res6, zero};
RegSum1:            TYPE = MACHINE DEPENDENT {
zero(0),        one(1),        two(2),        three(3),
minus4(4),    minus3(5),    minus2(6),    minus1(7),
op47(8),        alpha(9),        alpha03(10),    alpha47(11),
deltaS(12),    beta(13),        beta03(14),    beta47(15)};

<<These must agree with DragOpsCross.ProcessorRegister>>
stackTop:            Reg = [ s      , zero ];
constantZero:        Reg = [ cBase , zero ];
euField:            Reg = [ aBase , minus1 ];
inhibitStore:        Reg = [ aBase , minus4 ];
euGF:                Reg = [ aBase , zero ];
ifuXBus:            Reg = [ iRef  , minus4 ];
ifuLevel3LS:        Reg = [ iRef  , minus3 ];
ifuYoungestL:    Reg = [ iRef  , minus2 ];

IFUState: TYPE = RECORD [
delayed:                BOOL _ FALSE,
done:                    BOOL _ FALSE,
cycle:                    [0..64) _ 0,
rescheduleWaiting:    BOOL _ FALSE,    -- goes into trap PC generator
inhibitTraps:            BOOL _ FALSE,    -- disables reschedule and stack overflows
exceptions:            Exceptions        -- prioritized phase A exceptions
];

IFUStatusControl: TYPE = RECORD [
reschedule:    BitCont    _ nop,
inhibit:        BitCont    _ nop        -- prioritized phase A exceptions
];
BitCont: TYPE = {nop, clear, set};

<<Calculated during phA for use during phB.>>
MicroTrap: TYPE = RECORD [
trapPC:    Dragon.HexWord _ 0,
killPipe:    BOOL _ FALSE
];

<<Calculated during phB.>>
MicroInst: TYPE = RECORD [

<<Needed during the first PhB of the macro. Must be fast. May be unary.>>
aReg, bReg:        Reg _ constantZero,
getNextMacro:    BOOL _ TRUE, -- TRUE for last micro of sequential macro
xBSource:            XBSource _ pcPlusLen,
doMacroJump:    BOOL _ FALSE,
<<TRUE for some micro of jmps, calls, returns, & jmping Cjmps>>
<<>>
<<Needed during the following PhA.>>
cReg:                Reg _ inhibitStore,
lSource:            Reg _ [ l, zero ],
sSource:            Reg _ [ s, deltaS ],
deltaS:            [-2..1] _ 0,
xASource:        XASource _ none,
aluRtIsK:            BOOL _ FALSE,  -- True for Wt and many others
aluOp:            Dragon.ALUOps _ Or,
condSel:            Dragon.CondSelects _ False,
condEffect:        CondEffect _ macroTrap,
dontBypass:        BOOL _ FALSE, -- TRUE for EXCH
iStackPostEffect:    IStackPostEffect _ none,
iTrapPostEffect:    ITrapPostEffect _ none,
euPBusCmd:        Dragon.PBusCommands _ NoOp,
pipedPLSASpec:    PipedPLSASpec _ pls,
pushLevel3:        BOOL _ FALSE
];

DefaultMicro:    MicroInst = [];
NoOpMicro:        MicroInst = [ getNextMacro: FALSE, xBSource: pc ];

GetMicroInst: PROC [bArgs: PHBargs] RETURNS [ m: MicroInst, newState: IFUState];
PHBargs: TYPE = RECORD [
state                      :IFUState,
op                        :Dragon.Opcode,
alpha                    :Dragon.HexByte,
beta                    :Dragon.HexByte,
delayACycle            :BOOL, -- from pipeline interlocks or EU reject
iStkEmpty            :BOOL,
pushPending            :BOOL _ FALSE,
popPending            :BOOL _ FALSE,
instReady            :BOOL ];

GetMicroTrap: PROC [aArgs: PHAargs] RETURNS [ m: MicroTrap, newState: IFUState];
PHAargs: TYPE = RECORD [
state                      :IFUState,
ifuStatusControl        :IFUStatusControl, 
iTrapEffect3            :ITrapPostEffect _ none,
reset                    :BOOL _ FALSE,
reschedule            :BOOL _ FALSE,

preFetchFaulted        :BOOL _ FALSE, -- from IFetcher

pushPending            :BOOL _ FALSE,
popPending            :BOOL _ FALSE,
iTrapEffectPending    :ITrapPostEffect _ none,
iStkOverflow            :BOOL _ FALSE,
eStkOverflow        :BOOL _ FALSE, -- from IFU

aluCondResult2        :BOOL _ FALSE, -- input pin from EU
aluCond2                :Dragon.CondSelects _ False, -- from IFU pipeline
condEffect2            :CondEffect _ macroTrap, -- from IFU pipeline

pBusReject3            :BOOL,
pBusFault3            :Dragon.PBusFaults _ None ]

END.