DIRECTORY
RoseTypes, IFUInterlock, RoseCreate, Basics, IFUPLAInterlock, SwitchTypes, Dragon, IFUPLAMainControl;

IFUInterlockImpl: CEDAR PROGRAM
IMPORTS RoseCreate, Basics, IFUPLAInterlock
EXPORTS IFUInterlock

= BEGIN OPEN
RoseTypes, IFUInterlock;

ALULeftSources: TYPE = Dragon.ALULeftSources;
ALURightSources: TYPE = Dragon.ALURightSources;
Store2ASources: TYPE = Dragon.Store2ASources;
PBusCommands: TYPE = Dragon.PBusCommands;
CondSelects: TYPE = Dragon.CondSelects;
CondEffect: TYPE = IFUPLAMainControl.CondEffect;
ALUOps: TYPE = Dragon.ALUOps;
MicroExcptJmp: TYPE = IFUPLAMainControl.MicroExcptJmp;


RegisterCells: PROC =
BEGIN
Interlock _ RoseCreate.RegisterCellType[name: "Interlock",
expandProc: NIL,
ioCreator: CreateInterlockIO, driveCreator: CreateInterlockDrive, 
evals: [EvalSimple: InterlockEvalSimple],
tests: LIST[],
ports: CreateInterlockPorts[]
];
ControlPipe _ RoseCreate.RegisterCellType[name: "ControlPipe",
expandProc: NIL,
ioCreator: CreateControlPipeIO, driveCreator: CreateControlPipeDrive, initializer: InitializeControlPipe,
evals: [EvalSimple: ControlPipeEvalSimple],
tests: LIST[],
ports: CreateControlPipePorts[]
];
END;
otherss: SymbolTable _ RoseCreate.GetOtherss["IFUInterlock.partsAssertions"];
Interlock: PUBLIC CellType;

CreateInterlockPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUInterlock.Interlock.rosePorts"]};

InterlockSwitchIORef: TYPE = REF InterlockSwitchIORec;
InterlockSwitchIORec: TYPE = RECORD [
KIsRtOp1BA: SwitchTypes.SwitchVal
,FCtlIsRtOp1BA: SwitchTypes.SwitchVal
,C2IsFieldCtlAB: SwitchTypes.SwitchVal
,C3IsFieldCtlAB: SwitchTypes.SwitchVal
,DPCmndRd2BA: SwitchTypes.SwitchVal
,DPCmndRd3BA: SwitchTypes.SwitchVal
,ARegIsC2BA: SwitchTypes.SwitchVal
,ARegIsC3BA: SwitchTypes.SwitchVal
,BRegIsC2BA: SwitchTypes.SwitchVal
,BRegIsC3BA: SwitchTypes.SwitchVal
,Stage1BHoldBA: SwitchTypes.SwitchVal
,EUAluLeftSrc1B: PACKED ARRAY [0 .. 2) OF SwitchTypes.SwitchVal
,EUAluRightSrc1B: PACKED ARRAY [0 .. 3) OF SwitchTypes.SwitchVal
,EUStore2ASrc1B: PACKED ARRAY [0 .. 2) OF SwitchTypes.SwitchVal
,EUSt3AisCBus1BA: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

InterlockSimpleIORef: TYPE = REF InterlockSimpleIORec;
InterlockSimpleIORec: TYPE = RECORD [
fill0: [0 .. 32767],
KIsRtOp1BA: BOOLEAN
,fill1: [0 .. 32767],
FCtlIsRtOp1BA: BOOLEAN
,fill2: [0 .. 32767],
C2IsFieldCtlAB: BOOLEAN
,fill3: [0 .. 32767],
C3IsFieldCtlAB: BOOLEAN
,fill4: [0 .. 32767],
DPCmndRd2BA: BOOLEAN
,fill5: [0 .. 32767],
DPCmndRd3BA: BOOLEAN
,fill6: [0 .. 32767],
ARegIsC2BA: BOOLEAN
,fill7: [0 .. 32767],
ARegIsC3BA: BOOLEAN
,fill8: [0 .. 32767],
BRegIsC2BA: BOOLEAN
,fill9: [0 .. 32767],
BRegIsC3BA: BOOLEAN
,fill10: [0 .. 32767],
Stage1BHoldBA: BOOLEAN
,fill11: [0 .. 16383],
EUAluLeftSrc1B: ALULeftSources
,fill12: [0 .. 8191],
EUAluRightSrc1B: ALURightSources
,fill13: [0 .. 16383],
EUStore2ASrc1B: Store2ASources
,fill14: [0 .. 32767],
EUSt3AisCBus1BA: BOOLEAN
,fill15: [0 .. 32767],
PhA: BOOLEAN
,fill16: [0 .. 32767],
PhB: BOOLEAN
];

InterlockDriveRef: TYPE = REF InterlockDriveRec;
InterlockDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY InterlockPort OF DriveLevel];
InterlockPort: TYPE = {
KIsRtOp1BA, FCtlIsRtOp1BA, C2IsFieldCtlAB, C3IsFieldCtlAB, DPCmndRd2BA, DPCmndRd3BA, ARegIsC2BA, ARegIsC3BA, BRegIsC2BA, BRegIsC3BA, Stage1BHoldBA, EUAluLeftSrc1B, EUAluRightSrc1B, EUStore2ASrc1B, EUSt3AisCBus1BA, PhA, PhB, InterlockPortTypePad17, InterlockPortTypePad18, InterlockPortTypePad19};

CreateInterlockIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[InterlockSwitchIORec] ELSE NEW[InterlockSimpleIORec];
};

CreateInterlockDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[InterlockDriveRec];
};

InterlockEvalSimple: SimpleEval =
BEGIN
drive: InterlockDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: InterlockSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: InterlockSimpleIORef _ NARROW[cell.realCellStuff.newIO];
BEGIN OPEN drive, newIO;

IF PhB THEN {
[ [
stage1BHold:			Stage1BHoldBA,
aluLt:					EUAluLeftSrc1B,
aluRt:					EUAluRightSrc1B,
st2A:					EUStore2ASrc1B,
st3AIsCbus:			EUSt3AisCBus1BA
] ] _ IFUPLAInterlock.InterlockProc[ [

kIsRtOp:				KIsRtOp1BA,
fCtlIsRtOp:			FCtlIsRtOp1BA,
c2IsFieldCtl:			C2IsFieldCtlAB,
c3IsFieldCtl:			C3IsFieldCtlAB,

dpCmndRd2:			DPCmndRd2BA,
dpCmndRd3:			DPCmndRd3BA,
a1IsC2:				ARegIsC2BA,
a1IsC3:				ARegIsC3BA,
b1IsC2:				BRegIsC2BA,
b1IsC3:				BRegIsC3BA ] ];
drive[EUAluLeftSrc1B] _ drive;
drive[EUAluRightSrc1B] _ drive;
drive[EUStore2ASrc1B] _ drive;
}
ELSE {
drive[EUAluLeftSrc1B] _ ignore;
drive[EUAluRightSrc1B] _ ignore;
drive[EUStore2ASrc1B] _ ignore};

END;
END;


PCmdBitsOn: PROC [pcmd: Dragon.PBusCommands, bits: [0..256) ] RETURNS [ BOOL ] =
{RETURN[Basics.BITAND[pcmd.ORD, bits] = bits]};

ControlPipe: PUBLIC CellType;

CreateControlPipePorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUInterlock.ControlPipe.rosePorts"]};

ControlPipeSwitchIORef: TYPE = REF ControlPipeSwitchIORec;
ControlPipeSwitchIORec: TYPE = RECORD [
X2ASrcLit0BA: SwitchTypes.SwitchVal
,X2ASrcLit1BA: SwitchTypes.SwitchVal
,KIsRtOp0BA: SwitchTypes.SwitchVal
,KIsRtOp1BA: SwitchTypes.SwitchVal
,KPadsIn0BA: SwitchTypes.SwitchVal
,KPadsIn3BA: SwitchTypes.SwitchVal
,Push0BA: SwitchTypes.SwitchVal
,Push2BA: SwitchTypes.SwitchVal
,Push3BA: SwitchTypes.SwitchVal
,Pop0BA: SwitchTypes.SwitchVal
,Pop3BA: SwitchTypes.SwitchVal
,PushPendingAB: SwitchTypes.SwitchVal
,PopPendingAB: SwitchTypes.SwitchVal
,FCtlIsRtOp0BA: SwitchTypes.SwitchVal
,FCtlIsRtOp1BA: SwitchTypes.SwitchVal
,C0IsFieldCtlBA: SwitchTypes.SwitchVal
,C2IsFieldCtlAB: SwitchTypes.SwitchVal
,C3IsFieldCtlAB: SwitchTypes.SwitchVal
,CRegIsField3B: SwitchTypes.SwitchVal
,DPCmnd0BA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DPCmnd3A: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,EUWriteToPBus3AB: SwitchTypes.SwitchVal
,EURes3BisPBus3AB: SwitchTypes.SwitchVal
,DPCmndRd0BA: SwitchTypes.SwitchVal
,DPCmndRd2BA: SwitchTypes.SwitchVal
,DPCmndRd3BA: SwitchTypes.SwitchVal
,EUCondSel0BA: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,EUCondSel2AB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,EUCondSel3AB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,EUSt3AisCBus1BA: SwitchTypes.SwitchVal
,EUSt3AisCBus2BA: SwitchTypes.SwitchVal
,EUCondEffect0BA: PACKED ARRAY [0 .. 2) OF SwitchTypes.SwitchVal
,EUCondEffect1BA: PACKED ARRAY [0 .. 2) OF SwitchTypes.SwitchVal
,EUCondEffect2AB: PACKED ARRAY [0 .. 2) OF SwitchTypes.SwitchVal
,EUCondEffect2BA: PACKED ARRAY [0 .. 2) OF SwitchTypes.SwitchVal
,EStkOverflow1BA: SwitchTypes.SwitchVal
,EStkOverflow2BA: SwitchTypes.SwitchVal
,EUAluOp0BA: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,EUAluOp2AB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,DPRejectedBA: SwitchTypes.SwitchVal
,IPFaulted0BA: SwitchTypes.SwitchVal
,IPFaulted2BA: SwitchTypes.SwitchVal
,InstReadyAB: SwitchTypes.SwitchVal
,InstStarting0BA: SwitchTypes.SwitchVal
,InstStarting2BA: SwitchTypes.SwitchVal
,LoadStage1Ac: SwitchTypes.SwitchVal
,LoadStage1Bc: SwitchTypes.SwitchVal
,LoadStage2Ac: SwitchTypes.SwitchVal
,BubbleStage2A1BA: SwitchTypes.SwitchVal
,NormalStage2A1BA: SwitchTypes.SwitchVal
,AbortStage2B2AB: SwitchTypes.SwitchVal
,NormalStage2B2AB: SwitchTypes.SwitchVal
,LoadStage3Ac: SwitchTypes.SwitchVal
,AbortStage3A2BA: SwitchTypes.SwitchVal
,NormalStage3A2BA: SwitchTypes.SwitchVal
,MicroExcptJmpAB: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

ControlPipeSimpleIORef: TYPE = REF ControlPipeSimpleIORec;
ControlPipeSimpleIORec: TYPE = RECORD [
fill0: [0 .. 32767],
X2ASrcLit0BA: BOOLEAN
,fill1: [0 .. 32767],
X2ASrcLit1BA: BOOLEAN
,fill2: [0 .. 32767],
KIsRtOp0BA: BOOLEAN
,fill3: [0 .. 32767],
KIsRtOp1BA: BOOLEAN
,fill4: [0 .. 32767],
KPadsIn0BA: BOOLEAN
,fill5: [0 .. 32767],
KPadsIn3BA: BOOLEAN
,fill6: [0 .. 32767],
Push0BA: BOOLEAN
,fill7: [0 .. 32767],
Push2BA: BOOLEAN
,fill8: [0 .. 32767],
Push3BA: BOOLEAN
,fill9: [0 .. 32767],
Pop0BA: BOOLEAN
,fill10: [0 .. 32767],
Pop3BA: BOOLEAN
,fill11: [0 .. 32767],
PushPendingAB: BOOLEAN
,fill12: [0 .. 32767],
PopPendingAB: BOOLEAN
,fill13: [0 .. 32767],
FCtlIsRtOp0BA: BOOLEAN
,fill14: [0 .. 32767],
FCtlIsRtOp1BA: BOOLEAN
,fill15: [0 .. 32767],
C0IsFieldCtlBA: BOOLEAN
,fill16: [0 .. 32767],
C2IsFieldCtlAB: BOOLEAN
,fill17: [0 .. 32767],
C3IsFieldCtlAB: BOOLEAN
,fill18: [0 .. 32767],
CRegIsField3B: BOOLEAN
,fill19: [0 .. 255],
DPCmnd0BA: PBusCommands
,fill20: [0 .. 255],
DPCmnd3A: PBusCommands
,fill21: [0 .. 32767],
EUWriteToPBus3AB: BOOLEAN
,fill22: [0 .. 32767],
EURes3BisPBus3AB: BOOLEAN
,fill23: [0 .. 32767],
DPCmndRd0BA: BOOLEAN
,fill24: [0 .. 32767],
DPCmndRd2BA: BOOLEAN
,fill25: [0 .. 32767],
DPCmndRd3BA: BOOLEAN
,fill26: [0 .. 4095],
EUCondSel0BA: CondSelects
,fill27: [0 .. 4095],
EUCondSel2AB: CondSelects
,fill28: [0 .. 4095],
EUCondSel3AB: CondSelects
,fill29: [0 .. 32767],
EUSt3AisCBus1BA: BOOLEAN
,fill30: [0 .. 32767],
EUSt3AisCBus2BA: BOOLEAN
,fill31: [0 .. 16383],
EUCondEffect0BA: CondEffect
,fill32: [0 .. 16383],
EUCondEffect1BA: CondEffect
,fill33: [0 .. 16383],
EUCondEffect2AB: CondEffect
,fill34: [0 .. 16383],
EUCondEffect2BA: CondEffect
,fill35: [0 .. 32767],
EStkOverflow1BA: BOOLEAN
,fill36: [0 .. 32767],
EStkOverflow2BA: BOOLEAN
,fill37: [0 .. 4095],
EUAluOp0BA: ALUOps
,fill38: [0 .. 4095],
EUAluOp2AB: ALUOps
,fill39: [0 .. 32767],
DPRejectedBA: BOOLEAN
,fill40: [0 .. 32767],
IPFaulted0BA: BOOLEAN
,fill41: [0 .. 32767],
IPFaulted2BA: BOOLEAN
,fill42: [0 .. 32767],
InstReadyAB: BOOLEAN
,fill43: [0 .. 32767],
InstStarting0BA: BOOLEAN
,fill44: [0 .. 32767],
InstStarting2BA: BOOLEAN
,fill45: [0 .. 32767],
LoadStage1Ac: BOOLEAN
,fill46: [0 .. 32767],
LoadStage1Bc: BOOLEAN
,fill47: [0 .. 32767],
LoadStage2Ac: BOOLEAN
,fill48: [0 .. 32767],
BubbleStage2A1BA: BOOLEAN
,fill49: [0 .. 32767],
NormalStage2A1BA: BOOLEAN
,fill50: [0 .. 32767],
AbortStage2B2AB: BOOLEAN
,fill51: [0 .. 32767],
NormalStage2B2AB: BOOLEAN
,fill52: [0 .. 32767],
LoadStage3Ac: BOOLEAN
,fill53: [0 .. 32767],
AbortStage3A2BA: BOOLEAN
,fill54: [0 .. 32767],
NormalStage3A2BA: BOOLEAN
,fill55: [0 .. 4095],
MicroExcptJmpAB: MicroExcptJmp
,fill56: [0 .. 32767],
PhA: BOOLEAN
,fill57: [0 .. 32767],
PhB: BOOLEAN
];

ControlPipeDriveRef: TYPE = REF ControlPipeDriveRec;
ControlPipeDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY ControlPipePort OF DriveLevel];
ControlPipePort: TYPE = {
X2ASrcLit0BA, X2ASrcLit1BA, KIsRtOp0BA, KIsRtOp1BA, KPadsIn0BA, KPadsIn3BA, Push0BA, Push2BA, Push3BA, Pop0BA, Pop3BA, PushPendingAB, PopPendingAB, FCtlIsRtOp0BA, FCtlIsRtOp1BA, C0IsFieldCtlBA, C2IsFieldCtlAB, C3IsFieldCtlAB, CRegIsField3B, DPCmnd0BA, DPCmnd3A, EUWriteToPBus3AB, EURes3BisPBus3AB, DPCmndRd0BA, DPCmndRd2BA, DPCmndRd3BA, EUCondSel0BA, EUCondSel2AB, EUCondSel3AB, EUSt3AisCBus1BA, EUSt3AisCBus2BA, EUCondEffect0BA, EUCondEffect1BA, EUCondEffect2AB, EUCondEffect2BA, EStkOverflow1BA, EStkOverflow2BA, EUAluOp0BA, EUAluOp2AB, DPRejectedBA, IPFaulted0BA, IPFaulted2BA, InstReadyAB, InstStarting0BA, InstStarting2BA, LoadStage1Ac, LoadStage1Bc, LoadStage2Ac, BubbleStage2A1BA, NormalStage2A1BA, AbortStage2B2AB, NormalStage2B2AB, LoadStage3Ac, AbortStage3A2BA, NormalStage3A2BA, MicroExcptJmpAB, PhA, PhB, ControlPipePortTypePad58, ControlPipePortTypePad59};

CreateControlPipeIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[ControlPipeSwitchIORec] ELSE NEW[ControlPipeSimpleIORec];
};

CreateControlPipeDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[ControlPipeDriveRec];
};

ControlPipeStateRef: TYPE = REF ControlPipeStateRec;
ControlPipeStateRec: TYPE = RECORD [
ctlPipe0BA: RECORD [
instReady:		BOOL
],
ctlPipe1AB: RECORD [
x2ASrcLit:		BOOL,
push:				BOOL,
pop:				BOOL,
kPadsIn:			BOOL,
dpCmnd:			Dragon.PBusCommands,
aluOp:			Dragon.ALUOps,
kIsRtOp:			BOOL,
condSel:			Dragon.CondSelects,
condEffect:		IFUPLAMainControl.CondEffect,
fCtlIsRtOp: 		BOOL,
cBusIsFieldReg:	BOOL,
res3BisPBus:		BOOL,
writeToPBus:		BOOL,
instFault:			BOOL,
firstMicro:		BOOL
],
ctlPipe1BA: RECORD [
x2ASrcLit:		BOOL,
push:				BOOL,
pop:				BOOL,
kPadsIn:			BOOL,
dpCmnd:			Dragon.PBusCommands,
aluOp:			Dragon.ALUOps,
kIsRtOp:			BOOL,
condSel:			Dragon.CondSelects,
condEffect:		IFUPLAMainControl.CondEffect,
fCtlIsRtOp: 		BOOL,
cBusIsFieldReg:	BOOL,
res3BisPBus:		BOOL,
writeToPBus:		BOOL,
instFault:			BOOL,
firstMicro:		BOOL
],
ctlPipe2AB: RECORD [
x2ASrcLit:		BOOL,
push:				BOOL,
pop:				BOOL,
kPadsIn:			BOOL,
dpCmnd:			Dragon.PBusCommands,
aluOp:			Dragon.ALUOps,
condSel:			Dragon.CondSelects,
condEffect:		IFUPLAMainControl.CondEffect,
cBusIsFieldReg:	BOOL,
res3BisPBus:		BOOL,
writeToPBus:		BOOL,
eStkOverflow:	BOOL,
st3AisCBus:		BOOL,
instFault:			BOOL,
firstMicro:		BOOL
],
ctlPipe2BA: RECORD [
push:				BOOL,
pop:				BOOL,
kPadsIn:			BOOL,
dpCmnd:			Dragon.PBusCommands,
condSel:			Dragon.CondSelects,
condEffect:		IFUPLAMainControl.CondEffect,
cBusIsFieldReg:	BOOL,
res3BisPBus:		BOOL,
writeToPBus:		BOOL,
eStkOverflow:	BOOL,
st3AisCBus:		BOOL,
instFault:			BOOL,
firstMicro:		BOOL
],
ctlPipe3AB: RECORD [
push:				BOOL,
pop:				BOOL,
kPadsIn:			BOOL,
dpCmnd:			Dragon.PBusCommands,
condSel:			Dragon.CondSelects,
cBusIsFieldReg:	BOOL,
res3BisPBus:		BOOL,
writeToPBus:		BOOL
],
ctlPipe3BA: RECORD [
push:				BOOL,
pop:				BOOL,
kPadsIn:			BOOL,
cBusIsFieldReg:	BOOL,
res3BisPBus:		BOOL
]
];

InitializeControlPipe: Initializer = {
state: ControlPipeStateRef _ NEW[ControlPipeStateRec];
cell.realCellStuff.state _ state;
};

ControlPipeEvalSimple: SimpleEval =
BEGIN
drive: ControlPipeDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: ControlPipeSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: ControlPipeSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: ControlPipeStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;
IF PhB THEN ctlPipe0BA _ [
instReady: InstReadyAB
];

IF LoadStage1Ac THEN ctlPipe1AB _ [
x2ASrcLit:		X2ASrcLit0BA,
push:				Push0BA,
pop:				Pop0BA,
kPadsIn:			KPadsIn0BA,
dpCmnd:			DPCmnd0BA,
aluOp:			EUAluOp0BA,
kIsRtOp:			KIsRtOp0BA,
condSel:			EUCondSel0BA,
condEffect:		EUCondEffect0BA,
fCtlIsRtOp: 		FCtlIsRtOp0BA,
cBusIsFieldReg:	C0IsFieldCtlBA,
res3BisPBus:		DPCmndRd0BA,
writeToPBus:		PCmdBitsOn[DPCmnd0BA, Dragon.wrt],
instFault:			IPFaulted0BA AND NOT ctlPipe0BA.instReady,
firstMicro:		InstStarting0BA
];

IF LoadStage1Bc THEN ctlPipe1BA _ [
x2ASrcLit:		ctlPipe1AB.x2ASrcLit,
push:				ctlPipe1AB.push,
pop:				ctlPipe1AB.pop,
kIsRtOp:			ctlPipe1AB.kIsRtOp,
dpCmnd:			ctlPipe1AB.dpCmnd,
aluOp:			ctlPipe1AB.aluOp,
kPadsIn:			ctlPipe1AB.kPadsIn,
condSel:			ctlPipe1AB.condSel,
condEffect:		ctlPipe1AB.condEffect,
fCtlIsRtOp:		ctlPipe1AB.fCtlIsRtOp,
cBusIsFieldReg:	ctlPipe1AB.cBusIsFieldReg,
res3BisPBus:		ctlPipe1AB.res3BisPBus,
writeToPBus:		ctlPipe1AB.writeToPBus,
instFault:			ctlPipe1AB.instFault,
firstMicro:		ctlPipe1AB.firstMicro
];

IF LoadStage2Ac THEN ctlPipe2AB _ (SELECT TRUE FROM
NormalStage2A1BA => [
x2ASrcLit:		ctlPipe1BA.x2ASrcLit,
push:				ctlPipe1BA.push,
pop:				ctlPipe1BA.pop,
kPadsIn:			ctlPipe1BA.kPadsIn,
dpCmnd:			ctlPipe1BA.dpCmnd,
aluOp:			ctlPipe1BA.aluOp,
condSel:			ctlPipe1BA.condSel,
condEffect:		ctlPipe1BA.condEffect,
cBusIsFieldReg:	ctlPipe1BA.cBusIsFieldReg,
res3BisPBus:		ctlPipe1BA.res3BisPBus,
writeToPBus:		ctlPipe1BA.writeToPBus,
eStkOverflow:	EStkOverflow1BA,
st3AisCBus:		EUSt3AisCBus1BA,
instFault:			ctlPipe1BA.instFault,
firstMicro:		ctlPipe1BA.firstMicro
],
BubbleStage2A1BA => [
x2ASrcLit:		FALSE,
push:				FALSE,
pop:				FALSE,
kPadsIn:			FALSE,
dpCmnd:			NoOp,
aluOp:			Or,
condSel:			False,
condEffect:		bubble,
cBusIsFieldReg:	FALSE,
res3BisPBus:		FALSE,
writeToPBus:		FALSE,
eStkOverflow:	FALSE,
st3AisCBus:		FALSE,
instFault:			FALSE,
firstMicro:		FALSE
],
ENDCASE => ERROR);

IF PhB THEN ctlPipe2BA _ (SELECT TRUE FROM
NormalStage2B2AB =>
[
push:				ctlPipe2AB.push,
pop:				ctlPipe2AB.pop,
kPadsIn:			ctlPipe2AB.kPadsIn,
dpCmnd:			ctlPipe2AB.dpCmnd,
condSel:			ctlPipe2AB.condSel,
condEffect:		ctlPipe2AB.condEffect,
cBusIsFieldReg:	ctlPipe2AB.cBusIsFieldReg,
res3BisPBus:		ctlPipe2AB.res3BisPBus,
writeToPBus:		ctlPipe2AB.writeToPBus,
eStkOverflow:	ctlPipe2AB.eStkOverflow,
st3AisCBus:		ctlPipe2AB.st3AisCBus,
instFault:			ctlPipe2AB.instFault,
firstMicro:		ctlPipe2AB.firstMicro
],
AbortStage2B2AB => [
push:				FALSE,
pop:				FALSE,
kPadsIn:			FALSE,
dpCmnd:			NoOp,
condSel:			False,
condEffect:		bubble,
cBusIsFieldReg:	FALSE,
res3BisPBus:		FALSE,
writeToPBus:		FALSE,
eStkOverflow:	FALSE,
st3AisCBus:		FALSE,
instFault:			FALSE,
firstMicro:		FALSE
],
ENDCASE => ERROR);

IF LoadStage3Ac THEN ctlPipe3AB _ (SELECT TRUE FROM
NormalStage3A2BA => [
push:				ctlPipe2BA.push,
pop:				ctlPipe2BA.pop,
kPadsIn:			ctlPipe2BA.kPadsIn,
dpCmnd:			ctlPipe2BA.dpCmnd,
condSel:			ctlPipe2BA.condSel,
cBusIsFieldReg:	ctlPipe2BA.cBusIsFieldReg,
res3BisPBus:		ctlPipe2BA.res3BisPBus,
writeToPBus:		ctlPipe2BA.writeToPBus
],
AbortStage3A2BA => [
push:				FALSE,
pop:				FALSE,
kPadsIn:			FALSE,
dpCmnd:			NoOp,
condSel:			ctlPipe2BA.condSel,
cBusIsFieldReg:	FALSE,
res3BisPBus:		FALSE,
writeToPBus:		FALSE
],
ENDCASE => ERROR);

IF PhB THEN ctlPipe3BA _ [
push:				ctlPipe3AB.push OR (MicroExcptJmpAB = trap),
pop:				ctlPipe3AB.pop,
kPadsIn:			ctlPipe3AB.kPadsIn,
cBusIsFieldReg:	ctlPipe3AB.cBusIsFieldReg,
res3BisPBus:		ctlPipe3AB.res3BisPBus
];

PushPendingAB _ ctlPipe1AB.push OR ctlPipe2AB.push OR ctlPipe3AB.push;
PopPendingAB _ ctlPipe1AB.pop OR ctlPipe2AB.pop OR ctlPipe3AB.pop;

KIsRtOp1BA				_ ctlPipe1BA.kIsRtOp;
FCtlIsRtOp1BA			_ ctlPipe1BA.fCtlIsRtOp;
EUCondEffect1BA		_ ctlPipe1BA.condEffect;

X2ASrcLit1BA			_ ctlPipe2AB.x2ASrcLit;
EUAluOp2AB			_ ctlPipe2AB.aluOp;
EUCondSel2AB			_ ctlPipe2AB.condSel;
EUCondEffect2AB		_ ctlPipe2AB.condEffect;
C2IsFieldCtlAB			_ ctlPipe2AB.cBusIsFieldReg;

DPCmndRd2BA			_ ctlPipe2BA.res3BisPBus;
Push2BA					_ ctlPipe2BA.push;
EUCondEffect2BA		_ ctlPipe2BA.condEffect;
EStkOverflow2BA		_ ctlPipe2BA.eStkOverflow;
EUSt3AisCBus2BA		_ ctlPipe2BA.st3AisCBus;
IPFaulted2BA			_ ctlPipe2BA.instFault;
InstStarting2BA			_ ctlPipe2BA.firstMicro;

EUCondSel3AB			_ ctlPipe3AB.condSel;
DPCmnd3A				_ IF DPRejectedBA THEN NoOp ELSE ctlPipe3AB.dpCmnd;
EURes3BisPBus3AB		_ ctlPipe3AB.res3BisPBus;
EUWriteToPBus3AB		_ ctlPipe3AB.writeToPBus;
C3IsFieldCtlAB			_ ctlPipe3AB.cBusIsFieldReg;

DPCmndRd3BA			_ ctlPipe3BA.res3BisPBus;
Push3BA					_ ctlPipe3BA.push;
Pop3BA					_ ctlPipe3BA.pop;
KPadsIn3BA				_ ctlPipe3BA.kPadsIn;
drive[CRegIsField3B]	_ IF PhB THEN drive ELSE ignore;
CRegIsField3B			_ ctlPipe3BA.cBusIsFieldReg;

END;
END;

RegisterCells[];

END.

€IFUInterlockImpl.Mesa
created by RoseTranslate 3.1.3 of September 5, 1985 12:14:34 pm PDT
created from IFUInterlock.Rose of February 27, 1986 2:21:36 pm PST
created for McCreight.pa
created at March 10, 1986 7:06:10 pm PST
Signal Type decls
stage1BHoldIfReject:	Stage1BHoldIfRejectBA,
condEffect2:			EUCondEffect2AB,
explicitly requested CEDAR:
Advance Pipeline


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