DIRECTORY
RoseTypes, IFUData2LS, RoseCreate, Dragon, DragOpsCross, BitOps, SwitchTypes, IFUPLAInstrDecode;

IFUData2LSImpl: CEDAR PROGRAM
IMPORTS RoseCreate, BitOps
EXPORTS IFUData2LS

= BEGIN OPEN
RoseTypes, IFUData2LS;

LSourceLt: TYPE = IFUPLAInstrDecode.LSourceLt;
LSourceRt: TYPE = IFUPLAInstrDecode.LSourceRt;
SSourceLt: TYPE = IFUPLAInstrDecode.SSourceLt;
SSourceRt: TYPE = IFUPLAInstrDecode.SSourceRt;


RegisterCells: PROC =
BEGIN
LFormation _ RoseCreate.RegisterCellType[name: "LFormation",
expandProc: NIL,
ioCreator: CreateLFormationIO, driveCreator: CreateLFormationDrive, initializer: InitializeLFormation,
evals: [EvalSimple: LFormationEvalSimple],
tests: LIST[],
ports: CreateLFormationPorts[]
];
SDelta _ RoseCreate.RegisterCellType[name: "SDelta",
expandProc: NIL,
ioCreator: CreateSDeltaIO, driveCreator: CreateSDeltaDrive, 
evals: [EvalSimple: SDeltaEvalSimple],
tests: LIST[],
ports: CreateSDeltaPorts[]
];
SFormation _ RoseCreate.RegisterCellType[name: "SFormation",
expandProc: NIL,
ioCreator: CreateSFormationIO, driveCreator: CreateSFormationDrive, initializer: InitializeSFormation,
evals: [EvalSimple: SFormationEvalSimple],
tests: LIST[],
ports: CreateSFormationPorts[]
];
SLimitTest _ RoseCreate.RegisterCellType[name: "SLimitTest",
expandProc: NIL,
ioCreator: CreateSLimitTestIO, driveCreator: CreateSLimitTestDrive, initializer: InitializeSLimitTest,
evals: [EvalSimple: SLimitTestEvalSimple],
tests: LIST[],
ports: CreateSLimitTestPorts[]
];
END;
otherss: SymbolTable _ RoseCreate.GetOtherss["IFUData2LS.partsAssertions"];
LFormation: PUBLIC CellType;

CreateLFormationPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUData2LS.LFormation.rosePorts"]};

LFormationSwitchIORef: TYPE = REF LFormationSwitchIORec;
LFormationSwitchIORec: TYPE = RECORD [
AlphaBA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,SAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LStkTopAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LPipe3BA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LSourceLtBA: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,LSourceRtBA: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,LoadStage1Ac: SwitchTypes.SwitchVal
,LoadStage1Bc: SwitchTypes.SwitchVal
,LoadStage2Ac: SwitchTypes.SwitchVal
,LoadStage3Ac: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

LFormationSimpleIORef: TYPE = REF LFormationSimpleIORec;
LFormationSimpleIORec: TYPE = RECORD [
fill0: [0 .. 255],
AlphaBA: [0..255]
,fill1: [0 .. 255],
SAB: [0..255]
,fill2: [0 .. 255],
LStkTopAB: [0..255]
,fill3: [0 .. 255],
LAB: [0..255]
,fill4: [0 .. 255],
LPipe3BA: [0..255]
,fill5: [0 .. 4095],
LSourceLtBA: LSourceLt
,fill6: [0 .. 4095],
LSourceRtBA: LSourceRt
,fill7: [0 .. 32767],
LoadStage1Ac: BOOLEAN
,fill8: [0 .. 32767],
LoadStage1Bc: BOOLEAN
,fill9: [0 .. 32767],
LoadStage2Ac: BOOLEAN
,fill10: [0 .. 32767],
LoadStage3Ac: BOOLEAN
,fill11: [0 .. 32767],
PhA: BOOLEAN
,fill12: [0 .. 32767],
PhB: BOOLEAN
];

LFormationDriveRef: TYPE = REF LFormationDriveRec;
LFormationDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY LFormationPort OF DriveLevel];
LFormationPort: TYPE = {
AlphaBA, SAB, LStkTopAB, LAB, LPipe3BA, LSourceLtBA, LSourceRtBA, LoadStage1Ac, LoadStage1Bc, LoadStage2Ac, LoadStage3Ac, PhA, PhB, LFormationPortTypePad13, LFormationPortTypePad14, LFormationPortTypePad15};

CreateLFormationIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[LFormationSwitchIORec] ELSE NEW[LFormationSimpleIORec];
};

CreateLFormationDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[LFormationDriveRec];
};

LFormationStateRef: TYPE = REF LFormationStateRec;
LFormationStateRec: TYPE = RECORD [
lBA, lAB: Dragon.HexByte,
lPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte
];

InitializeLFormation: Initializer = {
state: LFormationStateRef _ NEW[LFormationStateRec];
cell.realCellStuff.state _ state;
};

LFormationEvalSimple: SimpleEval =
BEGIN
drive: LFormationDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: LFormationSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: LFormationSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: LFormationStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;
lBusLtB, lBusRtB: [0..256);
IF PhA THEN LAB _ lAB _ lBA;

IF PhB THEN {
lPipe[0][b] _ lAB;
lBusLtB _ SELECT LSourceLtBA FROM
l			=> LAB,
s			=> SAB,
zero		=> 0,
l3			=> lPipe[3][a],
ENDCASE	=> ERROR;
lBusRtB _ SELECT LSourceRtBA FROM
zero		=> 0,
alpha		=> AlphaBA,
stack		=> LStkTopAB,
one		=> 1,
ENDCASE	=> ERROR;
lBA	_ (lBusLtB + lBusRtB) MOD 128;
};

IF LoadStage1Ac THEN lPipe[1][a] _ lPipe[0][b];
IF LoadStage1Bc THEN lPipe[1][b] _ lPipe[1][a];
IF LoadStage2Ac THEN lPipe[2][a] _ lPipe[1][b];
IF PhB THEN lPipe[2][b] _ lPipe[2][a];
IF LoadStage3Ac THEN lPipe[3][a] _ lPipe[2][b];
IF PhB THEN lPipe[3][b] _ lPipe[3][a];

LPipe3BA _ lPipe[3][b];

END;
END;
SDelta: PUBLIC CellType;

CreateSDeltaPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUData2LS.SDelta.rosePorts"]};

SDeltaSwitchIORef: TYPE = REF SDeltaSwitchIORec;
SDeltaSwitchIORec: TYPE = RECORD [
PopSa0BA: SwitchTypes.SwitchVal
,PopSb0BA: SwitchTypes.SwitchVal
,PushSc0BA: SwitchTypes.SwitchVal
,DeltaSBA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
];

SDeltaSimpleIORef: TYPE = REF SDeltaSimpleIORec;
SDeltaSimpleIORec: TYPE = RECORD [
fill0: [0 .. 32767],
PopSa0BA: BOOLEAN
,fill1: [0 .. 32767],
PopSb0BA: BOOLEAN
,fill2: [0 .. 32767],
PushSc0BA: BOOLEAN
,fill3: [0 .. 255],
DeltaSBA: [0..255]
];

SDeltaDriveRef: TYPE = REF SDeltaDriveRec;
SDeltaDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY SDeltaPort OF DriveLevel];
SDeltaPort: TYPE = {
PopSa0BA, PopSb0BA, PushSc0BA, DeltaSBA};

CreateSDeltaIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[SDeltaSwitchIORec] ELSE NEW[SDeltaSimpleIORec];
};

CreateSDeltaDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[SDeltaDriveRec];
};

SDeltaEvalSimple: SimpleEval =
BEGIN
drive: SDeltaDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: SDeltaSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: SDeltaSimpleIORef _ NARROW[cell.realCellStuff.newIO];
BEGIN OPEN drive, newIO;
sum: INT;
sum		_ 0		+	(IF PushSc0BA	THEN 1 ELSE 0);
sum		_ sum	-	(IF PopSa0BA	THEN 1 ELSE 0);
sum		_ sum	-	(IF PopSb0BA	THEN 1 ELSE 0);
DeltaSBA	_ (sum	+ 256) MOD 256;
END;
END;
SFormation: PUBLIC CellType;

CreateSFormationPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUData2LS.SFormation.rosePorts"]};

SFormationSwitchIORef: TYPE = REF SFormationSwitchIORec;
SFormationSwitchIORec: TYPE = RECORD [
AlphaBA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,LAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,SAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,DeltaSBA: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,SSourceLtBA: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,SSourceRtBA: PACKED ARRAY [0 .. 4) OF SwitchTypes.SwitchVal
,LoadStage1Ac: SwitchTypes.SwitchVal
,LoadStage1Bc: SwitchTypes.SwitchVal
,LoadStage2Ac: SwitchTypes.SwitchVal
,LoadStage3Ac: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

SFormationSimpleIORef: TYPE = REF SFormationSimpleIORec;
SFormationSimpleIORec: TYPE = RECORD [
fill0: [0 .. 255],
AlphaBA: [0..255]
,fill1: [0 .. 255],
LAB: [0..255]
,fill2: [0 .. 255],
SAB: [0..255]
,fill3: [0 .. 255],
DeltaSBA: [0..255]
,fill4: [0 .. 4095],
SSourceLtBA: SSourceLt
,fill5: [0 .. 4095],
SSourceRtBA: SSourceRt
,fill6: [0 .. 32767],
LoadStage1Ac: BOOLEAN
,fill7: [0 .. 32767],
LoadStage1Bc: BOOLEAN
,fill8: [0 .. 32767],
LoadStage2Ac: BOOLEAN
,fill9: [0 .. 32767],
LoadStage3Ac: BOOLEAN
,fill10: [0 .. 32767],
PhA: BOOLEAN
,fill11: [0 .. 32767],
PhB: BOOLEAN
];

SFormationDriveRef: TYPE = REF SFormationDriveRec;
SFormationDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY SFormationPort OF DriveLevel];
SFormationPort: TYPE = {
AlphaBA, LAB, SAB, DeltaSBA, SSourceLtBA, SSourceRtBA, LoadStage1Ac, LoadStage1Bc, LoadStage2Ac, LoadStage3Ac, PhA, PhB};

CreateSFormationIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[SFormationSwitchIORec] ELSE NEW[SFormationSimpleIORec];
};

CreateSFormationDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[SFormationDriveRec];
};

SFormationStateRef: TYPE = REF SFormationStateRec;
SFormationStateRec: TYPE = RECORD [
sBA, sAB: Dragon.HexByte,
sPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexByte
];

InitializeSFormation: Initializer = {
state: SFormationStateRef _ NEW[SFormationStateRec];
cell.realCellStuff.state _ state;
};

SFormationEvalSimple: SimpleEval =
BEGIN
drive: SFormationDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: SFormationSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: SFormationSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: SFormationStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;
sBusLt, sBusRt:	Dragon.HexByte;

IF PhA THEN SAB _ sAB _ sBA;

IF PhB THEN {
sPipe[0][b] _ sAB;
sBusLt _ SELECT SSourceLtBA FROM
s			=>	SAB,
l			=>	LAB,
s2			=>	sPipe[2][a],
s3			=>	sPipe[3][a],
ENDCASE	=>	ERROR;

sBusRt _ SELECT SSourceRtBA FROM
deltaS		=>	DeltaSBA,
alpha		=>	AlphaBA,
zero		=>  0,
one		=>  1,
ENDCASE	=>	ERROR;

sBA _ (sBusLt+sBusRt+256) MOD 128;

};

IF LoadStage1Ac THEN sPipe[1][a] _  sPipe[0][b];
IF LoadStage1Bc THEN sPipe[1][b] _ sPipe[1][a];
IF LoadStage2Ac THEN sPipe[2][a] _ sPipe[1][b];
IF PhB THEN sPipe[2][b] _ sPipe[2][a];
IF LoadStage3Ac THEN sPipe[3][a] _ sPipe[2][b];

END;
END;
SLimitTest: PUBLIC CellType;

CreateSLimitTestPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["IFUData2LS.SLimitTest.rosePorts"]};

SLimitTestSwitchIORef: TYPE = REF SLimitTestSwitchIORec;
SLimitTestSwitchIORec: TYPE = RECORD [
XBus: PACKED ARRAY [0 .. 32) OF SwitchTypes.SwitchVal
,SAB: PACKED ARRAY [0 .. 8) OF SwitchTypes.SwitchVal
,EStkOverflow1BA: SwitchTypes.SwitchVal
,X1ASrcSLimitAc: SwitchTypes.SwitchVal
,X1ADstSLimitAc: SwitchTypes.SwitchVal
,PhA: SwitchTypes.SwitchVal
,PhB: SwitchTypes.SwitchVal
];

SLimitTestSimpleIORef: TYPE = REF SLimitTestSimpleIORec;
SLimitTestSimpleIORec: TYPE = RECORD [
XBus: ARRAY [0..2) OF CARDINAL
,fill1: [0 .. 255],
SAB: [0..255]
,fill2: [0 .. 32767],
EStkOverflow1BA: BOOLEAN
,fill3: [0 .. 32767],
X1ASrcSLimitAc: BOOLEAN
,fill4: [0 .. 32767],
X1ADstSLimitAc: BOOLEAN
,fill5: [0 .. 32767],
PhA: BOOLEAN
,fill6: [0 .. 32767],
PhB: BOOLEAN
];

SLimitTestDriveRef: TYPE = REF SLimitTestDriveRec;
SLimitTestDriveRec: TYPE = RECORD [driveRecordInitialPadding: DriveTagType, drive: PACKED ARRAY SLimitTestPort OF DriveLevel];
SLimitTestPort: TYPE = {
XBus, SAB, EStkOverflow1BA, X1ASrcSLimitAc, X1ADstSLimitAc, PhA, PhB, SLimitTestPortTypePad7};

CreateSLimitTestIO: PROC [ct: CellType, switch: BOOL] RETURNS [ioAsAny: REF ANY] --IOCreator-- = {
ioAsAny _ IF switch THEN NEW[SLimitTestSwitchIORec] ELSE NEW[SLimitTestSimpleIORec];
};

CreateSLimitTestDrive: PROC [ct: CellType] RETURNS [driveAsAny: REF ANY] --DriveCreator-- = {
driveAsAny _ NEW[SLimitTestDriveRec];
};

SLimitTestStateRef: TYPE = REF SLimitTestStateRec;
SLimitTestStateRec: TYPE = RECORD [
sLimitAB: 	        	Dragon.HexByte,
sLimitFromXBusBA: 	BOOL,
sLimitToXBusBA:        BOOL,
eStkOverflow1BA:		BOOL
];

InitializeSLimitTest: Initializer = {
state: SLimitTestStateRef _ NEW[SLimitTestStateRec];
cell.realCellStuff.state _ state;
};

SLimitTestEvalSimple: SimpleEval =
BEGIN
drive: SLimitTestDriveRef _ NARROW[cell.realCellStuff.newDriveAsAny];
sw: SLimitTestSwitchIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: SLimitTestSimpleIORef _ NARROW[cell.realCellStuff.newIO];
state: SLimitTestStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN drive, newIO, state;
IF X1ASrcSLimitAc THEN {drive[XBus] _ drive; XBus _ BitOps.ICID[sLimitAB, [0,0], 32, 24, 8]}
ELSE drive[XBus] _ ignore;

IF X1ADstSLimitAc THEN sLimitAB _ BitOps.ECFD[XBus, 32, 24, 8];

IF PhB THEN {
eStkOverflow1BA _ ((SAB+(255-sLimitAB --NOT sLimitAB-- )+1) MOD 128) IN [0..16);
};

EStkOverflow1BA _ eStkOverflow1BA;

END;
END;

RegisterCells[];

END.
ςIFUData2LSImpl.Mesa
created by RoseTranslate 3.1.3 of September 5, 1985 12:14:34 pm PDT
created from IFUData2LS.Rose of December 31, 1985 1:54:06 pm PST
created for McCreight.pa
created at March 10, 1986 7:03:19 pm PST
Signal Type decls
lPipe[i] is the value of the L register to be recovered if the microinstruction at pipeline level i "fails".  This assumes that each microinstruction can "fail" in only one way, and that that way is known as the microinstruction enters the pipeline.

Pipe
sPipe[i] is the value of the S register to be recovered if the microinstruction at pipeline level i "fails".  This assumes that each microinstruction can "fail" in only one way, and that that way is known as the microinstruction enters the pipeline.
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