Directory DragOpsCross, IFUPLAMainControl, IFUPLAInstrDecode; TranslationNeeds Dragon, IFUPLAMainControl, IFUPLAInstrDecode, IFUPLAFetchPreDecode; Imports DragonRoseExtras; CELLTYPE "X2ALitGen" PORTS [ XBus = INT[32], AlphaAB < INT[8], BetaAB < INT[8], GammaAB < INT[8], DeltaAB < INT[8], X2ALitSourceBA < EnumType["IFUPLAInstrDecode.X2ALitSource"], X2ASrcLit1BA < BOOL, LoadStage1Ac < BOOL, LoadStage1Bc < BOOL, LoadStage2Ac < BOOL, PhA AlphaAB, beta => BetaAB, alphaBeta => AlphaAB*LONG[256] + BetaAB, alpBetGamDel => ((AlphaAB*LONG[256] + BetaAB)*256 + GammaAB)*256 + DeltaAB, ENDCASE => AlphaAB -- don't care -- ; IF LoadStage1Ac THEN xaPipe1AB _ xaPipe0BA; IF LoadStage1Bc THEN xaPipe1BA _ xaPipe1AB; IF PhA AND X2ASrcLit1BA THEN { drive[XBus] _ drive; XBus _ DragonRoseExtras.LTD[xaPipe1BA] } ELSE drive[XBus] _ ignore; ENDCELLTYPE; CELLTYPE "PCForm" PORTS [ XBus < INT[32], -- address for SJ and SFC PCPipe3BA > INT[32], -- to Stack for calls, XOP's, and traps PCStkTopAB < INT[32], -- from Stack for returns PCBusB > INT[32], -- to Fetcher PCBusSrcB < EnumType["IFUPLAInstrDecode.PCBusSrc"], PCPipeSrcBA < EnumType["IFUPLAInstrDecode.PCPipeSrc"], PCNextBA < EnumType["IFUPLAInstrDecode.PCNext"], OpLengthBA < INT[3], JumpOffsetSelAB < EnumType["IFUPLAFetchPreDecode.JumpOffsetSel"], OpAB < INT[8], AlphaAB < INT[8], BetaAB < INT[8], GammaAB < INT[8], DeltaAB < INT[8], OpBA > INT[8], AlphaBA > INT[8], BetaBA > INT[8], LoadStage1Ac < BOOL, LoadStage1Bc < BOOL, LoadStage2Ac < BOOL, LoadStage3Ac < BOOL, AbortStage3A2BA < BOOL, NormalStage3A2BA < BOOL, ExceptionCodeAB < EnumType["IFUPLAMainControl.ExceptionCode"], DPFaultB < EnumType["Dragon.PBusFaults"], EUCondSel3AB < EnumType["Dragon.CondSelects"], PCForLogAB > INT[32], PhA < BOOL, PhB < BOOL ] State npcBA: Dragon.HexWord, -- latch on PCBusB pcSum: Dragon.HexWord, -- adder output pcBranchOSetB: Dragon.HexWord, -- mux for one arm of adder during PhB xAB: Dragon.HexWord, -- latch on XBus pcPipe: ARRAY [0..3] OF ARRAY Dragon.Phase OF Dragon.HexWord, pcAltPipe: ARRAY [0..2] OF ARRAY Dragon.Phase OF Dragon.HexWord, pcAB, pcBA: Dragon.HexWord, -- the PC for this instruction targetPCBA: Dragon.HexWord, dpFaultAB, dpFaultBA: Dragon.PBusFaults EvalSimple SExtnd: PROC[b: Dragon.HexByte] RETURNS [INT] = { RETURN[ IF b>=128 THEN (LONG[b]-256) ELSE LONG[b]] }; IF LoadStage1Ac THEN { pcPipe[1][a] _ pcBA; pcAltPipe[1][a] _ SELECT PCPipeSrcBA FROM seqPC => pcSum -- next sequential instruction -- , offSetPC => targetPCBA -- jump target instruction -- , thisPC => pcBA -- for traps that are recognized only at stage 0 -- , ENDCASE => ERROR; }; IF LoadStage1Bc THEN {pcPipe[1][b] _ pcPipe[1][a]; pcAltPipe[1][b] _ pcAltPipe[1][a]}; IF LoadStage2Ac THEN {pcPipe[2][a] _ pcPipe[1][b]; pcAltPipe[2][a] _ pcAltPipe[1][b]}; IF PhB THEN {pcPipe[2][b] _ pcPipe[2][a]; pcAltPipe[2][b] _ pcAltPipe[2][a]}; IF LoadStage3Ac THEN { pcPipe[3][a] _ (SELECT TRUE FROM AbortStage3A2BA => pcPipe[2][b], -- pc of aborting micro NormalStage3A2BA => pcAltPipe[2][b], -- whatever top of pipe suggested ENDCASE => ERROR) }; IF PhB THEN {pcPipe[3][b] _ pcPipe[3][a]}; PCPipe3BA _ DragonRoseExtras.LTD[pcPipe[3][b]]; IF PhA THEN { pcSum _ OpLengthBA + pcBA; pcAB _ SELECT PCNextBA FROM incr => pcSum, fromPCBus => npcBA, ENDCASE => ERROR; PCForLogAB _ DragonRoseExtras.LTD[pcAB]; xAB _ DragonRoseExtras.LFD[XBus]; dpFaultAB _ dpFaultBA; }; IF PhB THEN { pcBranchOSetB _ (SELECT JumpOffsetSelAB FROM alpha => SExtnd[AlphaAB], beta => SExtnd[BetaAB], alphaBeta => SExtnd[AlphaAB]*256 + BetaAB, xAB => xAB, ENDCASE => 0 -- shouldn't care, this will generate a jump-to-self so we'll notice -- ); targetPCBA _ pcSum _ pcBranchOSetB + pcAB; pcBA _ pcAB; PCBusB _ DragonRoseExtras.LTD[(npcBA _ (SELECT PCBusSrcB FROM offSetPC => pcSum, pc => pcAB, xA => xAB, xopGen => DragOpsCross.bytesPerWord*(DragOpsCross.XopBase + DragOpsCross.TrapWidthWords*OpAB), trapGen => DragOpsCross.bytesPerWord* (DragOpsCross.TrapBase+DragOpsCross.TrapWidthWords*( SELECT ExceptionCodeAB FROM cTrap => 20B -- = DragOpsCross.TrapIndex[ALUCondFalse].ORD -- +EUCondSel3AB.ORD, dpFault => 40B -- = DragOpsCross.TrapIndex[EUPageFault].ORD-1 -- +(dpFaultAB.ORD MOD 8), ENDCASE => ExceptionCodeAB.ORD MOD 20B)), alpBetGamDel => ((AlphaAB*LONG[256]+BetaAB)*256+GammaAB)*256+DeltaAB, pipe3 => DragonRoseExtras.LFD[PCPipe3BA], stack => DragonRoseExtras.LFD[PCStkTopAB], ENDCASE => ERROR))]; OpBA _ OpAB; AlphaBA _ AlphaAB; BetaBA _ BetaAB; dpFaultBA _ DPFaultB; }; ENDCELLTYPE ΚIFUData1.rose Curry, September 8, 1985 5:36:20 pm PDT Herrmann, September 12, 1985 6:27:48 pm PDT McCreight, March 18, 1986 5:35:29 pm PST Copyright c 1984 by Xerox Corporation. All rights reserved. Last edited by: McCreight, September 11, 1984 3:37:09 pm PDT Last edited by: Curry, January 15, 1985 11:35:15 am PST There are three PC values that may be needed for an instruction: the PC of the instruction itself, the PC of the next sequential instruction, and the PC of a call or jump target. The instruction PC is carried down pcPipe. One of the other two PC's, which may be needed as the return address of a call-type instruction or as the alternate PC of a failed conditional jump, is carried down altPcPipe. The third PC, if any, is passed immediately to the prefetcher. The two pipelined PC's merge at stage 3A, based on conditions computed at stage 2B. In the normal case, the merged value is altPc. In case of a trap or fault, the merged value is the pc of the offending instruction, carried in pcPipe. Memory reference instructions fail within stage 3, so they must specify PCLSPipeSrcBA = old. This shouldn't be a problem, since the only instructions that need to do otherwise are conditional jumps. Κ˜šΠbl ™ Icode™'K™+K™(™Jšœ Οmœ1™Jšœ œ˜—šœ’1˜@Jšœ  œ œ˜—Jš œ œ œ˜)——Jšœ œ'˜EJšœ,˜,Jšœ-˜-Jš œ œ˜J˜—Jšœ ˜ Jšœ˜Jšœ˜Jšœ˜Jšœ˜J˜J˜——Jš  ˜ ——…—Δ+