IFUStack.rose
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by: McCreight, March 11, 1986 11:50:41 am PST
Last edited by: Curry, September 5, 1985 11:21:45 pm PDT
Herrmann, September 12, 1985 2:53:40 pm PDT
Directory Dragon, DragOpsCross;
Imports BitOps, IFUPLAStackControl;
CELLTYPE "StackControl"
PORTS [
Push3BA    < BOOL, -- from ControlPipe
Pop3BA    < BOOL,
X1ASrcStackBA  < BOOL, -- from InstrDecode
X1ADstStackBA  < BOOL,
XBusStackEldestBA < BOOL, -- otherwise youngest
XBusStackLBA  < BOOL, -- otherwise PC
TosAB    < INT[5], -- unused
BosAB    < INT[5], -- unused
DifBA    < INT[5], -- Tos-Bos = -1 means empty, 0 means single entry, > nearlyFullDepth means nearlyFull
IStkNearlyFullBA > BOOL,  -- to MainControl
AdjTosA    > BOOL,  -- to StackPtrs
AddendIsOnesA  > BOOL,
CarryIsOneA   > BOOL,
StkLdLAc   > INT[16], -- to StkBuffer
StkLdPAc    > INT[16],
StkRdAc    > INT[16],
PhA     < BOOL,
PhB     < BOOL
]
State
stkLdPBA: IFUPLAStackControl.SixteenBits,
stkLdLBA: IFUPLAStackControl.SixteenBits,
stkRdBA: IFUPLAStackControl.SixteenBits
EvalSimple
IF PhA THEN {
[[
adjTos: AdjTosA,
addendIsOnes: AddendIsOnesA,
carryIsOne: CarryIsOneA
]] ← IFUPLAStackControl.StackAControlProc[[
diff: DifBA, -- unused
x1ASrcStack: X1ASrcStackBA,
x1ADstStack: X1ADstStackBA,
xBusStackEldest: XBusStackEldestBA,
xBusStackL: XBusStackLBA,
push3: Push3BA,
pop3: Pop3BA
]];
StkLdLAc ← stkLdLBA;
StkLdPAc ← stkLdPBA;
StkRdAc ← stkRdBA;
}
ELSE {StkLdLAc ← StkLdPAc ← StkRdAc ← 0};
IF PhB THEN {
[[
iStkNearlyFull: IStkNearlyFullBA
]] ← IFUPLAStackControl.StackBControlProc[[
diff: DifBA,
x1ASrcStack: X1ASrcStackBA, -- unused
x1ADstStack: X1ADstStackBA, -- unused
xBusStackEldest: XBusStackEldestBA, -- unused
xBusStackL: XBusStackLBA, -- unused
push3: Push3BA,
pop3: Pop3BA -- unused
]];
[[
stkLdP: stkLdPBA,
stkLdL: stkLdLBA,
stkRd: stkRdBA
]] ← IFUPLAStackControl.StackDecodeProc[[
tos: TosAB,
bos: BosAB,
diff: DifBA, -- unused
x1ASrcStack: X1ASrcStackBA,
x1ADstStack: X1ADstStackBA,
xBusStackEldest: XBusStackEldestBA,
xBusStackL: XBusStackLBA,
push3: Push3BA,
pop3: Pop3BA
]];
};
ENDCELLTYPE;
CELLTYPE "StackPtrs"
PORTS [
AdjTosA    < BOOL,  -- from StackControl
AddendIsOnesA  < BOOL,
CarryIsOneA   < BOOL,
TosAB    > INT[5], -- Tos=Bos-1 means empty, Tos=Bos means one entry
BosAB    > INT[5],
DifBA    > INT[5],
ResetBA    < BOOL,
PhA     < BOOL,
PhB     < BOOL ]
State
tosAB, tosBA: [0..32),
bosAB, bosBA: [0..32),
difBA: [0..32)
EvalSimple
IF PhA THEN {
adderMuxA: [0..32) = IF AdjTosA THEN tosBA ELSE bosBA;
addendA: [0..32) = IF AddendIsOnesA THEN 31 ELSE 0;
carryA: [0..1] = IF CarryIsOneA THEN 1 ELSE 0;
sumA: [0..32) = (adderMuxA+addendA+carryA) MOD 32;
TosAB ← tosAB ← SELECT TRUE FROM
ResetBA => 0,
AdjTosA => sumA,
ENDCASE => tosBA; -- needed because AdjTosA might glitch
BosAB ← bosAB ← SELECT TRUE FROM
ResetBA => 1,
NOT AdjTosA => sumA,
ENDCASE => bosBA; -- needed because AdjTosA might glitch
};
IF PhB THEN {
DifBA ← difBA ← (32+tosAB-bosAB) MOD 32;
tosBA ← tosAB;
bosBA ← bosAB;
};
ENDCELLTYPE;
CELLTYPE "WriteStackLEna"
PORTS [
X1ADstStackBA  < BOOL,  -- from InstrDecode
XBusStackEldestBA < BOOL,
XBusStackLBA  < BOOL,
TosAB    < INT[5],  -- from StackPtrs
BosAB    < INT[5],
Push3BA    < BOOL,
PhA     < BOOL,
PhB     < BOOL ]
State
stkLdLBA: PACKED ARRAY [0..16) OF BOOL
EvalSimple
IF PhB THEN {
stkLdLBA ← ALL[FALSE];
SELECT TRUE FROM
NOT X1ADstStackBA AND Push3BA => stkLdLBA[(TosAB+1) MOD 16] ← TRUE;
X1ADstStackBA AND XBusStackLBA AND XBusStackEldestBA =>
stkLdLBA[BosAB MOD 16] ← TRUE;
X1ADstStackBA AND XBusStackLBA AND NOT XBusStackEldestBA =>
stkLdLBA[TosAB MOD 16] ← TRUE;
ENDCASE => NULL;
};
StkLdLAc ← IF PhA THEN LOOPHOLE[stkLdLBA] ELSE 0;
ENDCELLTYPE;
CELLTYPE "WriteStackPEna"
PORTS [
X1ADstStackBA  < BOOL,  -- from InstrDecode
XBusStackEldestBA < BOOL,
XBusStackLBA  < BOOL,
TosAB    < INT[5],  -- from StackPtrs
BosAB    < INT[5],
Push3BA    < BOOL,
PhA     < BOOL,
PhB     < BOOL ]
State
stkLdPBA: PACKED ARRAY [0..16) OF BOOL
EvalSimple
IF PhB THEN {
stkLdPBA ← ALL[FALSE];
SELECT TRUE FROM
NOT X1ADstStackBA AND Push3BA => stkLdPBA[(TosAB+1) MOD 16] ← TRUE;
X1ADstStackBA AND NOT XBusStackLBA AND XBusStackEldestBA =>
stkLdPBA[BosAB MOD 16] ← TRUE;
X1ADstStackBA AND NOT XBusStackLBA AND NOT XBusStackEldestBA =>
stkLdPBA[TosAB MOD 16] ← TRUE;
ENDCASE => NULL;
};
StkLdPAc ← IF PhA THEN LOOPHOLE[stkLdPBA] ELSE 0;
ENDCELLTYPE;
CELLTYPE "ReadStackEna"
PORTS [
X1ASrcStackBA  < BOOL,  -- from InstrDecode
XBusStackEldestBA < BOOL,
TosAB    < INT[5],  -- from StackPtrs
BosAB    < INT[5],
Pop3BA    < BOOL,
PhA     < BOOL,
PhB     < BOOL ]
State
stkRdBA: PACKED ARRAY [0..16) OF BOOL
EvalSimple
IF PhB THEN {
stkRdBA ← ALL[FALSE];
SELECT TRUE FROM
NOT X1ASrcStackBA AND NOT Pop3BA,
X1ASrcStackBA AND NOT XBusStackEldestBA =>
stkRdBA[TosAB MOD 16] ← TRUE;
NOT X1ASrcStackBA AND Pop3BA => stkRdBA[(TosAB+31) MOD 16] ← TRUE;
X1ASrcStackBA AND XBusStackEldestBA => stkRdBA[BosAB MOD 16] ← TRUE;
ENDCASE => ERROR;
};
StkRdAc ← IF PhA THEN LOOPHOLE[stkRdBA] ELSE 0;
ENDCELLTYPE;
CELLTYPE "StackBuffer"
PORTS [
XBus     = INT[32],
PCPipe3BA   < INT[32], -- PCHandler
PCStkTopAB   > INT[32],
LPipe3BA   < INT[8],  -- LPipe
LStkTopAB   > INT[8],
X1ASrcStackBA  < BOOL, -- from InstrDecode
X1ADstStackBA  < BOOL,
XBusStackEldestBA < BOOL,  -- otherwise youngest
XBusStackLBA  < BOOL,  -- otherwise PC
StkRdAc    < INT[16],
StkLdLAc   < INT[16], 
StkLdPAc    < INT[16],
Push3BA    < BOOL, -- for pipeline bypass
PhA     < BOOL,
PhB     < BOOL
]
State
pStack:     ARRAY [0..16) OF Dragon.HexWord,
pRdBufA, pWrtBufA: Dragon.HexWord,
lStack:     ARRAY [0..16) OF Dragon.HexByte,
lRdBufA, lWrtBufA: Dragon.HexByte
EvalSimple
IF X1ADstStackBA THEN {
pWrtBufA ← BitOps.ELFD[XBus, 32, 0, 32];
lWrtBufA ← BitOps.ELFD[XBus, 32, 24, 8];
}
ELSE {
pWrtBufA ← BitOps.ELFD[PCPipe3BA, 32, 0, 32];
lWrtBufA ← LPipe3BA;
};
FOR index: NAT IN [0..16) DO
EB: PROC[w: BitOps.BitWord] RETURNS[BOOL] =
{TRUSTED{RETURN[LOOPHOLE[w, PACKED ARRAY [0..16) OF BOOL][index]]}};
IF EB[StkRdAc] THEN {lRdBufA ← lStack[index]; pRdBufA ← pStack[index]};
IF EB[StkLdLAc] THEN lStack[index] ← lWrtBufA;
IF EB[StkLdPAc] THEN pStack[index] ← pWrtBufA;
ENDLOOP;
IF Push3BA THEN {pRdBufA ← pWrtBufA; lRdBufA ← lWrtBufA}; -- bypass
IF PhA AND X1ASrcStackBA THEN {
drive[XBus] ← drive;
XBus ← BitOps.ILID[(IF XBusStackLBA THEN lRdBufA ELSE pRdBufA), XBus, 32, 0, 32];
} ELSE drive[XBus] ← ignore;
IF PhA THEN {PCStkTopAB ← BitOps.ILID[pRdBufA, PCStkTopAB, 32, 0, 32]; LStkTopAB ← lRdBufA};
ENDCELLTYPE;
CELLTYPE "Stack"
PORTS [
XBus     = INT[32],
PCPipe3BA   < INT[32],
PCStkTopAB   > INT[32],
LPipe3BA   < INT[8],
LStkTopAB   > INT[8],
LBusB    > INT[8],
Push3BA    < BOOL,  -- from ControlPipe
Pop3BA    < BOOL,
X1ASrcStackBA  < BOOL,  -- from InstrDecode
X1ADstStackBA  < BOOL,
XBusStackEldestBA < BOOL,
XBusStackLBA  < BOOL,
IStkNearlyFullBA  > BOOL,  -- to MainControl
ResetBA    < BOOL,
PhA     < BOOL,
PhB     < BOOL
]
Expand
DifBA:    INT[5]; -- StackPtrs to StackControl
AdjTosA:    BOOL; -- StackControl to StackPtrs
AddendIsOnesA:  BOOL;
CarryIsOneA:  BOOL;
TosAB:    INT[5]; -- StackPtrs to WriteStack*Ena, ReadStackEna
BosAB:    INT[5];
StkLdPAc:   INT[16]; -- WriteStackPEna to StackBuffer
StkLdLAc:   INT[16]; -- WriteStackLEna to StackBuffer
StkRdAc:    INT[16]; -- ReadStackEna to StackBuffer
stackControl:   StackControl[];
stackPtrs:    StackPtrs[];
writeStackPEna:  WriteStackPEna[]; -- address decoder
writeStackLEna:  WriteStackLEna[]; -- address decoder
readStackEna:  ReadStackEna[]; -- address decoder
stackBuffer:   StackBuffer[]  -- data column
ENDCELLTYPE