<> <> <> <> <<>> <> <> <> Directory Dragon, IFUPLAInstrDecode; TranslationNeeds Dragon, IFUPLAMainControl, IFUPLAInstrDecode; Imports IFUPLAMainControl; CELLTYPE "MainControl" PORTS [ <<>> ResetBA < BOOL, DPRejectedBA < BOOL, DPFaultB < EnumType["Dragon.PBusFaults"], EUCondition2B < BOOL, EUCondEffect1BA < EnumType["IFUPLAMainControl.CondEffect"], EUCondEffect2BA < EnumType["IFUPLAMainControl.CondEffect"], Stage1BHoldBA < BOOL, <> InstStarting2BA < BOOL, IPFaulted2BA < BOOL, TrapsEnbled2BA < BOOL, RschWaiting2BA < BOOL, IStkNearlyFullBA < BOOL, EStkOverflow2BA < BOOL, Push2BA < BOOL, MicroCycleAB < INT[8], MicroCycleNextBA < EnumType["IFUPLAInstrDecode.MicroCycleNext"], MicroExcptJmpAB > EnumType["IFUPLAMainControl.MicroExcptJmp"], ExceptionCodeAB > EnumType["IFUPLAMainControl.ExceptionCode"], LoadStage1Ac > BOOL, -- Pipe Controls LoadStage1Bc > BOOL, LoadStage2Ac > BOOL, BubbleStage2A1BA > BOOL, NormalStage2A1BA > BOOL, AbortStage2B2AB > BOOL, NormalStage2B2AB > BOOL, LoadStage3Ac > BOOL, AbortStage3A2BA > BOOL, -- carries a weakened micro to stage 3AB for state-saving NormalStage3A2BA > BOOL, PhA < BOOL, PhB < BOOL ] State wantNewMicro0AB, wantNewMicro0BA: BOOL, stage1BHoldingAB: BOOL, wereResetAB, wereResetBA: BOOL, abortPipeAB, abortPipeBA: BOOL, dpFaultedBA: BOOL, euCondition2BA: BOOL, stage2FailedBA: BOOL, willBeProtMicroCycBA: BOOL EvalSimple IF PhA THEN { [ [ abortPipe: abortPipeAB, microExcptJmp: MicroExcptJmpAB, exceptionCode: ExceptionCodeAB ] ] _ IFUPLAMainControl.MainControlProc[ [ reseting: ResetBA, protMicroCyc: willBeProtMicroCycBA, dpFaulted: dpFaultedBA, dpRejected: DPRejectedBA, euCondition2: euCondition2BA, euCondEffect2: EUCondEffect2BA, stage1Hold: Stage1BHoldBA, <> condEffect1: EUCondEffect1BA, instStarting2: InstStarting2BA, ipFaulted2: IPFaulted2BA, trapsEnbled2: TrapsEnbled2BA, rschlWaiting2: RschWaiting2BA, eStkOverflow2: EStkOverflow2BA, iStkNearlyFull2: IStkNearlyFullBA, push2: Push2BA ] ]; wantNewMicro0AB _ MicroExcptJmpAB # bubble; <> stage1BHoldingAB _ EUCondEffect1BA # bubble AND (Stage1BHoldBA OR (DPRejectedBA -- AND Stage1BHoldIfRejectBA -- )); wereResetAB _ ResetBA; }; IF PhB THEN { wantNewMicro0BA _ wantNewMicro0AB; dpFaultedBA _ DPFaultB # none; euCondition2BA _ EUCondition2B; wereResetBA _ wereResetAB; abortPipeBA _ abortPipeAB; willBeProtMicroCycBA _ MicroCycleAB>=112 AND (MicroCycleNextBA = next); }; stage2FailedBA _ ResetBA OR abortPipeBA OR (EUCondEffect2BA=macroTrap AND euCondition2BA) OR IPFaulted2BA OR (TrapsEnbled2BA AND (EStkOverflow2BA OR (InstStarting2BA AND RschWaiting2BA) OR (Push2BA AND IStkNearlyFullBA) )); LoadStage1Ac _ PhA AND wantNewMicro0BA; LoadStage1Bc _ PhB AND (NOT stage1BHoldingAB OR ResetBA); LoadStage2Ac _ PhA AND (NOT (DPRejectedBA -- AND Stage1BHoldIfRejectBA -- ) OR ResetBA); BubbleStage2A1BA _ Stage1BHoldBA OR stage2FailedBA; NormalStage2A1BA _ NOT BubbleStage2A1BA; AbortStage2B2AB _ abortPipeAB; NormalStage2B2AB _ NOT AbortStage2B2AB; LoadStage3Ac _ PhA AND (NOT DPRejectedBA OR ResetBA); AbortStage3A2BA _ stage2FailedBA; NormalStage3A2BA _ NOT AbortStage3A2BA; ENDCELLTYPE; CELLTYPE "MicroCycle" PORTS [ MicroCycleAB > INT[8], MicroCycleNextBA < EnumType["IFUPLAInstrDecode.MicroCycleNext"], MicroExcptJmpAB < EnumType["IFUPLAMainControl.MicroExcptJmp"], -- CycleAB _ fix, excep, cycle ExceptionCodeAB < EnumType["IFUPLAMainControl.ExceptionCode"], PhA < BOOL, PhB < BOOL ] State microCycleAB, microCycleBA: Dragon.HexByte EvalSimple IF PhA THEN { microCycleAB _ microCycleBA; MicroCycleAB _ SELECT MicroExcptJmpAB FROM microCycleBA, microJump => 64, ENDCASE => 112+4*(MicroExcptJmpAB.ORD-IFUPLAMainControl.MicroExcptJmp[bubble].ORD); }; IF PhB THEN microCycleBA _ SELECT MicroCycleNextBA FROM clear => 0, hold => microCycleAB, next => MicroCycleAB +1, ENDCASE => ERROR; ENDCELLTYPE