
<<IFUPLA.mesa>>
<<Copyright © 1984 by Xerox Corporation.  All rights reserved.>>
<<Last edited by Twilliams, August 27, 1984 6:28:59 pm PDT>>
<<Last edited by Curry, January 15, 1985 11:41:20 am PST>>

DIRECTORY
Dragon,
DragOpsCross,
IO,
PLAOps;

IFUPLA: CEDAR DEFINITIONS =
BEGIN

MainControlProc:         PROC[args: MainControlIn]     RETURNS[result: MainControlOut];
InstrDecodeProc:         PROC[args: InstrDecodeIn]         RETURNS[result: InstrDecodeOut];
FetchControlProc:     PROC[args: FetchControlIn]     RETURNS[result: FetchControlOut];
FetchPreDecodeProc:     PROC[args: FetchPreDecodeIn]  RETURNS[result: FetchPreDecodeOut];

MainControlIn: TYPE = RECORD [    -- default must be zero for use initializing sigificance arg
reseting:                BOOL                    _  FALSE,
wereReseting:        BOOL                    _  FALSE,

epFaulted:            BOOL                    _  FALSE,
fpFaulted:            BOOL                    _  FALSE,
rejected:                BOOL                    _  FALSE,

aluCondResult2:        BOOL                    _  FALSE,
condEffect2:            CondEffect            _  LOOPHOLE[0],

noBypassing:            BOOL                    _  FALSE,
pCmndLev1Rd:        BOOL                    _  FALSE,
pCmndLev2Rd:        BOOL                    _  FALSE,
notPassRtIfAZero:    BOOL                    _  FALSE,
aluOpFOP:            BOOL                    _  FALSE,
kIsRtOp:                BOOL                    _  FALSE,
cRegIsField:            BOOL                    _  FALSE,
aRegIsZero:            BOOL                    _  FALSE,
aRegIsC2:                BOOL                    _  FALSE,
aRegIsC3:                BOOL                    _  FALSE,
bRegIsC2:                BOOL                    _  FALSE,
bRegIsC3:                BOOL                    _  FALSE,

instrDone:            BOOL                    _  FALSE,
instrDelayed:            BOOL                    _  FALSE,
getNextMacro:        BOOL                    _  FALSE,
macroJump:            BOOL                    _  FALSE,
ipFaulted:            BOOL                    _  FALSE,
trapsEnbled:            BOOL                    _  FALSE,
rschlWaiting:        BOOL                    _  FALSE,
iStkOverflow:        BOOL                    _  FALSE,
pushPending:        BOOL                    _  FALSE,
popPending:            BOOL                    _  FALSE,
eStkOverFlow:        BOOL                    _  FALSE ];

MainControlOut: TYPE = RECORD [
microBranch:            BOOL _ FALSE,
exception:            BOOL _ FALSE,
exceptionCode:        ExceptionCode _ 0,    -- new state is either this exception code or cycle #
delayNextInstr:        BOOL _ FALSE,

pipeAdv0:            BOOL _ FALSE,
pipeAdv1:            BOOL _ FALSE,    -- not (pipeCycle123 or pipeKill1)
pipeAdv2:            BOOL _ FALSE,    -- not (pipeCycle123 or pipeKill2)
pipeAdv3:            BOOL _ FALSE,    -- not (pipeCycle123 or pipeCCTrap3 or pipeFault3
pipeCycle123:        BOOL _ FALSE,
pipeKill1:                BOOL _ FALSE,
pipeKill2:                BOOL _ FALSE,
pipeCCTrap3:            BOOL _ FALSE,
pipeFault3:            BOOL _ FALSE,

aluLt:                    Dragon.ALULeftSources    _ aBus,
aluRt:                    Dragon.ALURightSources    _ bBus,
st2A:                    Dragon.Store2ASources        _ bBus,
st3AIsCbus:            BOOL _ FALSE,
res3AIsCbus:            BOOL _ FALSE,
res3BIsRdData:        BOOL _ FALSE
];

InstrDecodeIn: TYPE = RECORD [    -- default must be zero for use initializing sigificance arg

cycle:                Dragon.HexByte _ 0,
exception:        BOOL _ FALSE,
delayNextInstr:    BOOL _ FALSE,
instReady:        BOOL _ FALSE,
op:                DragOpsCross.Inst _ LOOPHOLE[0],
alpha:                Dragon.HexByte _ 0,
beta:                Dragon.HexByte _ 0,
iStkEmpty:        BOOL _ FALSE,
pushPending:    BOOL _ FALSE,
popPending:        BOOL _ FALSE,
userMode:        BOOL _ FALSE ];

InstrDecodeOut: TYPE = RECORD [
aReg:                    ABReg                        _ constantZero,
bReg:                    ABReg                        _ constantZero,
microJump:            BOOL                            _ FALSE,
macroJump:            BOOL                            _ FALSE,
dontGetNextMacro:    BOOL                            _ FALSE,
instrDelayed:         BOOL                            _ FALSE,
pcBusSrc:                PCBusSrc                        _ pc,
pcNext:                PCNext                        _ pcBus,
pclsPipeSrc:            PCLSPipeSrc                    _ old,
cReg:                    CReg                            _ inhibitStore,
lSource:                LSource                        _ [ l, zero ],
sSource:                SSource                        _ [ s, deltaS ],
popSa:                    BOOL                            _ FALSE,
popSb:                BOOL                            _ FALSE,
pushSc:                BOOL                            _ FALSE,
xASource:            XaSource                        _ none,
kIsRtOp:                BOOL                            _ FALSE,
aluOp:                Dragon.ALUOps                _ Or,
notPassRtIfAZero:    BOOL                            _ FALSE,
aluOpFOP:            BOOL                            _ FALSE,
condSel:                Dragon.CondSelects            _ False,
condEffect:            CondEffect                    _ macroTrap,
noBypassing:            BOOL                            _ FALSE, -- TRUE for EXCH
push:                    BOOL                            _ FALSE,
pop:                    BOOL                            _ FALSE,
euPCmnd:                Dragon.PBusCommands        _ NoOp,

fpCSLdAlu:                BOOL                        _ FALSE,
fpCSLdMult:                BOOL                        _ FALSE,
fpCSUnldAlu:            BOOL                        _ FALSE,
fpCSUnldMult:            BOOL                        _ FALSE,
fpCheckStatue:            BOOL                        _ FALSE,

changeTrapsEnbledBA:    BOOL                        _ FALSE,
changeUserModeBA:    BOOL                        _ FALSE,
changeFPAluArgBA:    BOOL                        _ FALSE,
changeFPMultArgBA:    BOOL                        _ FALSE,
newTrapsEnbledBA:    BOOL                        _ FALSE,
newUserModeBA:        BOOL                        _ FALSE,
newFPAluArgBA:        FPArgType                _ clear,
newFPMultArgBA:        FPArgType                _ clear
];

DefaultMicro:    InstrDecodeOut = [];
BlankMicro:        InstrDecodeOut = [];
NoOpMicro:        InstrDecodeOut =
[dontGetNextMacro: TRUE, pcBusSrc: pc, pcNext: pcBus];
Delayed:            InstrDecodeOut =
[dontGetNextMacro: TRUE, pcBusSrc: pc, pcNext: pcBus, instrDelayed: TRUE];

FetchControlIn: TYPE = RECORD [    -- default must be zero for use initializing sigificance arg
jump:                BOOL _ FALSE,
getNext:            BOOL _ FALSE,
hold:                BOOL _ FALSE,
reject:                BOOL _ FALSE,
jumping:            BOOL _ FALSE,
jumpInProgress:    BOOL _ FALSE,
jumpPending:    BOOL _ FALSE,
fetching:            BOOL _ FALSE,
roomFor1:            BOOL _ FALSE,
roomFor2:            BOOL _ FALSE,
faulted:            BOOL _ FALSE,
fault:                Dragon.PBusFaults    _ None,
opLength:        [0..7]                    _  LOOPHOLE[0],
offSet:                [0..3]                    _  LOOPHOLE[0]
];

FetchControlOut: TYPE = RECORD [-- default must be zero
jumpInProgress:    BOOL _ FALSE,
jumpPending:    BOOL _ FALSE,
newFetch:        BOOL _ FALSE,
fetching:            BOOL _ FALSE,
faulted:            BOOL _ FALSE,
incrPrefetch:        BOOL _ FALSE,
wt:                WtIndexCtl    _ [ ],
rd:                    RdIndexCtl    _ [ ]
];

FetchPreDecodeIn: TYPE = RECORD [    -- default must be zero
preOp:        DragOpsCross.Inst _ LOOPHOLE[0],
atLeast1:        BOOL _ FALSE,
atLeast2:        BOOL _ FALSE,
atLeast3:        BOOL _ FALSE,
atLeast5:        BOOL _ FALSE
];

FetchPreDecodeOut: TYPE = RECORD [-- default must be zero
instReady:            BOOL _ FALSE,
opLength:            [0..7] _ 0,
pcBranchOffSet:        PCBranchOffSet _ [ ]
];

WtIndexCtl: TYPE = RECORD[
set0:    BOOL _ FALSE,
inc0:    BOOL _ FALSE,
inc1:    BOOL _ FALSE ];

RdIndexCtl: TYPE = RECORD[
set0:    BOOL _ FALSE,
set1:    BOOL _ FALSE,
set2:    BOOL _ FALSE,
set3:    BOOL _ FALSE,
inc0:    BOOL _ FALSE,
inc1:    BOOL _ FALSE,
inc2:    BOOL _ FALSE,
inc3:    BOOL _ FALSE,
inc5:    BOOL _ FALSE ];

PCBranchOffSet: TYPE = RECORD[    -- should probably just decode opcode directly
alphaBeta:    BOOL _ FALSE,
beta:            BOOL _ FALSE,
alpha:            BOOL _ FALSE,
abgd:            BOOL _ FALSE ];

fixedMicroBranch: Dragon.HexByte = 64;

ExceptionCode: TYPE = Dragon.HexByte;
prioritySig        :ExceptionCode    = 10B;    -- 1xxx test used to identify these in PLA-B
exceptionSig        :ExceptionCode    = 07B;    -- 1xxx test used to identify these in PLA-B
highPriority        :ExceptionCode    = 10B;    -- 1xxx test used to identify these in PLA-B
<<High priority (not delayed by an interlock)>>
reseting        :ExceptionCode    = 17B;
reset            :ExceptionCode    = 16B;
epFault        :ExceptionCode    = 13B;
fpFault        :ExceptionCode    = 12B;
euCC            :ExceptionCode    = 11B;
cJump        :ExceptionCode    = 10B;
<<Low priority (happen at or below the priority of delayNextInstr generated in phA)>>
modeFault    :ExceptionCode    = 05B;    -- 
iFtchFault    :ExceptionCode    = 04B;    -- 
rschlWait        :ExceptionCode    = 02B;
iStkOFlow    :ExceptionCode    = 01B;
eStkOFlow    :ExceptionCode    = 00B;

CondEffect:            TYPE = MACHINE DEPENDENT {macroTrap(0),macroJump,microJump,res(3)};
IStackPostEffect:        TYPE = MACHINE DEPENDENT {none(0), push, pop, res(3)};
TrappingControl:    TYPE = MACHINE DEPENDENT {noChange(0), enable, disable, res(3)};
FPArgType:            TYPE = MACHINE DEPENDENT {clear, single, integer, double};

PCBusSrc: TYPE = MACHINE DEPENDENT
{pc(0), offSetPC, stack, delGamBetAlp, xA, pipe3, trapGen, xopGen};
PCNext: TYPE = MACHINE DEPENDENT {seqPC(0), pcBus(1)};
PCLSPipeSrc: TYPE = MACHINE DEPENDENT
{holdLastEntry(0), old(1), seqPCnewLS(2), offSetPCnewLS(3)};

XaSource:        TYPE = MACHINE DEPENDENT {
none(0),
alpha(8),                beta(9),                betaAlpha(10),    delGamBetAlp(11),
bReg(12),    -- This just means Lev1Dr nop
reserve15,
fpUnldMsw(16),        fpLdBSgl(17),        fpLdBMsw(18),        fpLdBLsw(19),
fpUnldLsw(20),        fpLdASgl(21),        fpLdAMsw(22),        fpLdALsw(23)};
<<This arrangement allows the constant generator to operate off the low 4 bits.  Bit 3 doubles as the level1XBusDr control.  Bit 4 
is the level2XBusDr control.  The euSwap BOOL must be specified separately. The constants below can be used in PLA's using XaSource 
as an input type.>>
constSig:        XaSource = reserve15;        -- low 4 bits
xALev1Dr:    XaSource = alpha;
xALev2Dr:    XaSource = fpUnldMsw;    -- 16

ABReg:        TYPE = RECORD [ lt: ABSourceLt, rt: ABSourceRt ]; -- 7 bits
ABSourceLt:    TYPE = MACHINE DEPENDENT {cBase(0), aBase, s, l, iRef, zero};
ABSourceRt:    TYPE = MACHINE DEPENDENT {
zero(0),        one(1),        two(2),        three(3),
minus4(4),    minus3(5),    minus2(6),    minus1(7),
op47(8),        alpha(9),        alpha03(10),    alpha47(11),
deltaS(12),    beta(13),        beta03(14),    beta47(15)};
CReg: TYPE = RECORD [ lt: CSourceLt, rt: CSourceRt ]; -- 7 bits
CSourceLt:    TYPE = MACHINE DEPENDENT {aBase(0), cBase, l, s, zero, iRef};
CSourceRt:    TYPE = MACHINE DEPENDENT {-- addr bit 1 invrtd from ABSourceRt
minus4(0),    minus3(1),    minus2(2),    minus1(3),
zero(4),        one(5),        two(6),        three(7),
deltaS(8),        beta(9),        beta03(10),    beta47(11),
op47(12),        alpha(13),    alpha03(14),    alpha47(15)};
LSource: TYPE = RECORD [ lt: LSourceLt, rt: LSourceRt ]; -- 4 bits
LSourceLt:            TYPE = MACHINE DEPENDENT {l(0), s, zero, l3};
LSourceRt:            TYPE = MACHINE DEPENDENT { zero(0), alpha, stack, one};
SSource: TYPE = RECORD [ lt: SSourceLt, rt: SSourceRt ]; -- 4 bits
SSourceLt:            TYPE = MACHINE DEPENDENT {s(0), l, zero, s3};
SSourceRt:            TYPE = MACHINE DEPENDENT { deltaS(0), alpha, zero, one};

<<These must agree with DragOpsCross.ProcessorRegister>>
abStackTop:        ABReg    = [ s      , zero ];
cStackTop:        CReg        = [ s      , zero ];
constantZero:        ABReg    = [ cBase , zero ];
euField:            CReg        = [ aBase , minus1 ];
inhibitStore:        CReg        = [ aBase , minus4 ];
euGF:                ABReg    = [ aBase , zero ];
ifuXBus:            CReg        = [ iRef  , minus4 ];

byteIsSig:            Dragon.HexByte = 377B;
byteNotSig:        Dragon.HexByte = 000B;
byteBot7NotSig:    Dragon.HexByte = 200B;
byteBot6NotSig:    Dragon.HexByte = 300B;

instrIsSig:            DragOpsCross.Inst = LOOPHOLE[377B];
instrBot1NotSig:    DragOpsCross.Inst = LOOPHOLE[376B];
instrBot3NotSig:    DragOpsCross.Inst = LOOPHOLE[370B];
instrBot4NotSig:    DragOpsCross.Inst = LOOPHOLE[360B];
instrBot5NotSig:    DragOpsCross.Inst = LOOPHOLE[340B];
instrBot6NotSig:    DragOpsCross.Inst = LOOPHOLE[300B];

<<Used by InstrDecode>>
current:                    PLAOps.BoolExpr;
GenInstrDecodePLA1:    PROC;
GenInstrDecodePLA2:    PROC;
GenInstrDecodePLA3:    PROC;
GenInstrDecodePLA4:    PROC;
BE:    PROC [m, d: InstrDecodeIn] RETURNS[PLAOps.BoolExpr];
Set:    PROC [s: PLAOps.BoolExpr _ NIL, m, d: InstrDecodeIn _ [ ], out: InstrDecodeOut];

ControlPipeRec: TYPE = RECORD [    -- ~35 bits - This is an aid to the ControlPipe Rose sim
drXa2Lev:        BOOL                            _ FALSE,
drXa3Lev:        BOOL                            _ FALSE,
push:                BOOL                            _ FALSE,
pop:                BOOL                            _ FALSE,
epCmnd:            Dragon.PBusCommands        _ NoOp,
fpCSUnAlu:        BOOL                            _ FALSE,
fpCSUnMult:        BOOL                            _ FALSE,
fpCheckStatus:    BOOL                            _ FALSE,
fpCSLdAlu:        BOOL                            _ FALSE,
fpCSLdMult:        BOOL                            _ FALSE,
aluLeftSrc:        Dragon.ALULeftSources    _ aBus,
aluRightSrc:        Dragon.ALURightSources    _ bBus,
store2ASrc:        Dragon.Store2ASources        _ bBus,
aluOp:            Dragon.ALUOps                _ Or,
condSel:            Dragon.CondSelects            _ False,
st3AisCBus:        BOOL                            _ FALSE,
res3AisCBus:        BOOL                            _ FALSE,
condEffect:        CondEffect                    _ macroTrap,
checkParity:        BOOL                            _ FALSE,
writeToPBus:        BOOL                            _ FALSE,
res3BisPBus:        BOOL                            _ FALSE ];

IFUStatusRec: TYPE = MACHINE DEPENDENT RECORD [
rescheduleSet    (0: 0.. 0):    BOOL            _ FALSE,
reschedule        (0: 1.. 1):    BOOL            _ FALSE,
reschedulePad    (0: 2.. 3):    [0..4)            _ 0,
trapsEnabledSet    (0: 4.. 4):    BOOL            _ FALSE,
trapsEnabled        (0: 5.. 5):    BOOL            _ FALSE,
trapsEnabledPad    (0: 6.. 7):    [0..4)            _ 0,
userModeSet        (0: 8.. 8):    BOOL            _ FALSE,
userMode            (0: 9.. 9):    BOOL            _ FALSE,
userModePad        (0:10..11):    [0..4)            _ 0,
fpArgAluSet        (0:12..12):    BOOL            _ FALSE,
fpArgAlu        (0:13..14):    FPArgType    _ clear,
fpArgAluPad    (0:15..15):    BOOL            _ FALSE,
fpArgMultSet    (0:16..16):    BOOL            _ FALSE,
fpArgMult        (0:17..18):    FPArgType    _ clear,
fpArgMulPad    (0:19..31):    [0..8192)        _ 0 ];

END.