[_CD4_]<dragon>ifu>IFUPLA>IFUPLAMainControlImpl.mesa!15

IFUPLAMainControlImpl.mesa

Last edited by Curry, May 13, 1986 7:46:36 pm PDT

McCreight, February 28, 1986 12:03:45 pm PST

DIRECTORY

Commander,

Dragon,

DragOpsCross,

IFUPLAMainControl,

IO,

PLAOps;

IFUPLAMainControlImpl: CEDAR PROGRAM

IMPORTS Commander, IO, PLAOps =

BEGIN OPEN IFUPLAMainControl, PLAOps;

MainControlPLA: PLAOps.PLA;

MainControlProc: PROC[args: MainControlIn] RETURNS[result: MainControlOut];

condEffectNotSig: CondEffect ← FIRST [CondEffect];

condEffectIsSig: CondEffect ← LAST [CondEffect];

pBusFaultNotSig: Dragon.PBusFaults ← FIRST [Dragon.PBusFaults];

pBusFaultIsSig: Dragon.PBusFaults ← LAST [Dragon.PBusFaults];

forceBubble: MainControlOut = [microExcptJmp: bubble, exceptionCode: bubble];

GenMainControlPLA: PROC = {

cur, temp: BoolExpr;

euStkOverflow: BoolExpr ← And[

BEX[[trapsEnbled2: TRUE]],

BEX[[eStkOverflow2: TRUE]]

];

ifuStkOverflow: BoolExpr ← And[

BEX[[trapsEnbled2: TRUE]],

BEX[[iStkNearlyFull2: TRUE]],

Or[

BEX[[dpFaulted: TRUE]],

And[

BEXNot[[dpRejected: TRUE]],

Or[

BEX[[push2: TRUE]],

BEX[[eStkOverflow2: TRUE]],

BEX[[ipFaulted2: TRUE]],

And[BEX[[instStarting2: TRUE]], BEX[[rschlWaiting2: TRUE]]],

And[

BEX[[euCondition2: TRUE]],

BE[ m: [euCondEffect2: condEffectIsSig], d: [euCondEffect2: macroTrap] ]

]

];

interlock: BoolExpr ← And[

Or[

BEX[[stage1Hold: TRUE]],

And[

BEX[[stage1HoldIfReject: TRUE]],

BEX[[dpRejected: TRUE]]

]

],

Not[BE[m: [condEffect1: condEffectIsSig], d: [condEffect1: bubble]]]

];

Reset

Set[m:[reseting: TRUE], d:[reseting: TRUE], out:[

abortPipe: TRUE,

microExcptJmp: resetting,

exceptionCode: reset ] ];

cur ← BEXNot[[reseting: TRUE]];

Intermediate cycle of protected microinstruction sequence

Set[s:cur, m:[protMicroCyc: TRUE], d:[protMicroCyc: TRUE], out:[

microExcptJmp: none,

exceptionCode: none ] ];

cur ← And[cur, BEXNot[[protMicroCyc: TRUE]]];

IFU stack overflow

Set[s: And[cur, ifuStkOverflow], out:[

abortPipe: TRUE,

microExcptJmp: trap,

exceptionCode: iStkOFlow ] ];

cur ← And[cur, Not[ifuStkOverflow]];

Data PBus Fault, pipe stage 3

Set[s:cur, m:[dpFaulted: TRUE], d:[dpFaulted: TRUE], out:[

abortPipe: TRUE,

microExcptJmp: trap,

exceptionCode: dpFault ] ];

cur ← And[cur, BEXNot[[dpFaulted: TRUE]]];

Reject

Set[s: And[cur, BEX[[dpRejected: TRUE]], interlock], out: forceBubble ];

cur ← And[cur, BEXNot[[dpRejected: TRUE]]];

ALU Condition, pipe stage 2

temp ← And[cur, BEX[[euCondition2: TRUE]]];

Set[s:temp, m:[euCondEffect2: condEffectIsSig], d:[euCondEffect2: macroTrap], out:[

abortPipe: TRUE,

microExcptJmp: trap,

exceptionCode: cTrap ] ];

Set[s:temp, m:[euCondEffect2: condEffectIsSig], d:[euCondEffect2: macroJump], out:[

abortPipe: TRUE,

microExcptJmp: cJump,

exceptionCode: cJump ] ];

Set[s:temp, m:[euCondEffect2: condEffectIsSig], d:[euCondEffect2: microJump], out:[

microExcptJmp: microJump ] ];

cur ← And[cur, BEXNot[[euCondition2: TRUE]]];

EU stack overflow, pipe stage 2

Set[s: And[cur, euStkOverflow], out:[

abortPipe: TRUE,

microExcptJmp: trap,

exceptionCode: eStkOFlow ] ];

cur ← And[cur, Not[euStkOverflow]];

Pipe Interlock

Set[s: And[cur, interlock], out: forceBubble ];

cur ← And[cur, Not[interlock]];

cur ← And[cur, BEX[[instStarting2: TRUE]] ];

Reschedule Waiting, pipe stage 2

Set[s: And[cur, BEX[[trapsEnbled2: TRUE]]], m:[rschlWaiting2: TRUE], d:[rschlWaiting2: TRUE], out:[

abortPipe: TRUE,

microExcptJmp: trap,

exceptionCode: rschlWait ]];

cur ← And[cur, Or[BEXNot[[rschlWaiting2: TRUE]], BEXNot[[trapsEnbled2: TRUE]]]];

Instruction Fetch Fault, pipe stage 2

Set[s:cur, m:[ipFaulted2: TRUE], d:[ipFaulted2: TRUE], out:[

abortPipe: TRUE,

microExcptJmp: trap,

exceptionCode: ipFault ]];

cur ← And[cur, BEXNot[[ipFaulted2: TRUE]]];

ELSE new unexceptional microinstruction [ ]

};

BE: PROC [m, d: MainControlIn ] RETURNS[ BoolExpr ] = {

mRef: REF MainControlIn ← NARROW[MainControlPLA.mask];

dRef: REF MainControlIn ← NARROW[MainControlPLA.data];

mRef^ ← m; dRef^ ← d; RETURN[GetBEForDataMask[MainControlPLA]]};

BEX: PROC [ d: MainControlIn ] RETURNS[ BoolExpr ] = { RETURN[ BE[d,d] ] };

BEXNot: PROC [ d: MainControlIn ] RETURNS[ BoolExpr ] = { RETURN[ BE[d,[]] ] };

Set: PROC [s: BoolExpr ← NIL, m, d: MainControlIn ← [ ], out: MainControlOut] = {

res: REF MainControlOut ← NARROW[MainControlPLA.out];

IF s=NIL

THEN s ← BE[m,d]

ELSE s ← And[s, BE[m,d] ];

res^ ← out; SetOutForBE[MainControlPLA, s]};

GenMainControl: Commander.CommandProc = {

filename: IO.ROPE ← DefaultCMDLine[cmd.commandLine, defaultFile];

MainControlPLA ← NewPLA["IFUPLAMainControl.MainControlIn", "IFUPLAMainControl.MainControlOut"];

GenMainControlPLA[];

[ ] ← ConvertTermListToCompleteSum[MainControlPLA.termList, FALSE, FALSE, cmd.out];

[ ] ← FindAMinimalCover[MainControlPLA.termList, 120, cmd.out];

WritePLAFile[filename, cmd.out, MainControlPLA] };

doc: IO.ROPE = "Expects the name of the ttt file";

defaultFile: IO.ROPE = "IFUPLAMainControl.ttt";

Commander.Register[key:"GenMainControl", proc: GenMainControl, doc: doc];

END.