reseting:    BOOL     ← FALSE,

protMicroCyc:  BOOL     ← FALSE,

dpFaulted:   BOOL     ← FALSE,

dpRejected:   BOOL     ← FALSE,

euCondition2:   BOOL     ← FALSE,

euCondEffect2:  CondEffect   ← LOOPHOLE[0],

stage1Hold:   BOOL     ← FALSE,

stage1HoldIfReject: BOOL     ← FALSE,

condEffect1:   CondEffect   ← VAL[0], -- for detecting bubble in 1B

instStarting2:   BOOL     ← FALSE,

ipFaulted2:   BOOL     ← FALSE,

trapsEnbled2:  BOOL     ← FALSE,

rschlWaiting2:  BOOL     ← FALSE,

eStkOverflow2:  BOOL     ← FALSE,

iStkNearlyFull2:  BOOL     ← FALSE,

push2:    BOOL     ← FALSE ];

abortPipe:     BOOL    ← FALSE,

microExcptJmp:   MicroExcptJmp ← none,

exceptionCode:   ExceptionCode ← none

];

..            type  index (2 lsb's of type = trap quad)

none   (0),     --  00 00 0000 no trap

ipFault  (special+1),   --  10 00 0001  type[1..3] specs trap PC formation

bubble  (special+2),   --  10 00 0010

cJump  (special+3),   --  10 00 0011

reseting  (special+6),   --  10 00 0110

reset   (special+7),   --  10 00 0111

iStkOFlow (special+8),   --  10 00 1000

eStkOFlow (special+9),   --  10 00 1001

rschlWait  (special+0AH),  --  10 00 1010

trapCycle1 (special+0BH),  --  10 00 1011 follows trapCycle0

cTrap   (special+cCode),  --  11 01 0000 use CCSelCode as index

dpFault  (special+dpFlt)  --  11 10 0000 use DPBusFault as index

};

special: [0..0FFH] = 80H;

cCode: [0..0FFH] = 50H;

dpFlt: [0..0FFH] = 60H;

The type can be coded as {0, 1} or {0, 1, 2, 4, 8 ...} or {0, 3, 5, 9, 17 ...}.

The first and last cases have the advantage that zero can be used a default multiplex control (lsb = 0 => no other bit is true).

In all cases it's possible to name the bits and/or their inverses using the enumerated type element names.

{macroTrap(0), macroJump, microJump, bubble(3)};

none(0), -- microcycle as proposed by instrDecode

microJump(3), -- microcycle = 64

bubble(5), -- microcycle = 112

resetting(9), -- microcycle = 116

trap(17), -- microcycle = 120

cJump(33) -- microcycle = 124

};