<> <> <> <> <<>> DIRECTORY Dragon, PLAOps; IFUPLAInterlock: CEDAR DEFINITIONS = BEGIN <> InterlockIn: TYPE = RECORD [ -- default must be zero <> kIsRtOp1: BOOL _ FALSE, -- describes the micro at stage 1B fCtlIsRtOp1: BOOL _ FALSE, cIsField2: BOOL _ FALSE, cIsField3: BOOL _ FALSE, dPCmndIsRd2: BOOL _ FALSE, -- micro at stage 2B generates PBus read a1IsC2: BOOL _ FALSE, a1IsC3: BOOL _ FALSE, b1IsC2: BOOL _ FALSE, b1IsC3: BOOL _ FALSE ]; InterlockOut: TYPE = RECORD [ stage1BHold: BOOL _ FALSE, <> eUAluLeftSrc1: Dragon.ALULeftSources _ aBus, -- if 1B will advance eUAluRightSrc1: Dragon.ALURightSources _ bBus, eUStore2ASrc1: Dragon.Store2ASources _ bBus, eUSt3AIsCBus1: BOOL _ FALSE ]; END.