IFUPLAInterlock.mesa
Copyright c 1984 by Xerox Corporation. All rights reserved.
Last edited by Curry, August 27, 1986 7:14:58 pm PDT
McCreight, December 19, 1985 4:41:50 pm PST
DIRECTORY
Dragon,
PLAOps;
IFUPLAInterlock: CEDAR DEFINITIONS =
BEGIN
This is BA logic: it computes during PhB using inputs that may be changing during PhB, and its outputs are stable by the end of PhB and can be captured in a PhB latch if necessary. Because its inputs may change during B, it should be implemented either as a static PLA or as an Alps cell.
InterlockIn: TYPE = RECORD [ -- default must be zero
condEffect2:  IFUPLAMainPipeControl.CondEffect ← VAL[0], -- for detecting bubble in 2B
kIsRtOp1:    BOOL     ← FALSE, -- describes the micro at stage 1B
fCtlIsRtOp1:   BOOL     ← FALSE,
cIsField2:    BOOL     ← FALSE,
cIsField3:    BOOL     ← FALSE,
dPCmndIsRd2:  BOOL     ← FALSE, -- micro at stage 2B generates PBus read
a1IsC2:    BOOL     ← FALSE,
a1IsC3:    BOOL     ← FALSE,
b1IsC2:    BOOL     ← FALSE,
b1IsC3:    BOOL     ← FALSE ];
InterlockOut: TYPE = RECORD [
stage1BHold:   BOOL       ← FALSE,
stage1BHoldIfReject: BOOL       ← FALSE,
eUAluLeftSrc1:  Dragon.ALULeftSources ← aBus, -- if 1B will advance
eUAluRightSrc1:  Dragon.ALURightSources ← bBus,
eUStore2ASrc1:  Dragon.Store2ASources  ← bBus,
eUSt3AIsCBus1:  BOOL ← FALSE
];
END.