
<<EU1Test.mesa>>
    <<Copyright © 1985 by Xerox Corporation.  All rights reserved.>>
    <<Gasbarro January 16, 1986 10:16:11 am PST>>
    <<Barth, January 22, 1986 6:03:25 pm PST>>
    <<Last Edited by: Gasbarro March 20, 1986 5:58:21 pm PST>>
    <<Louis Monier February 5, 1986 5:14:49 pm PST>>

    DIRECTORY
        Basics, Commander, Core, CoreOps, CoreCreate, EU1TestData, IO, ICTest, Ports, Rope, TerminalIO;


    EU1Test: CEDAR PROGRAM
    IMPORTS Basics, IO, CoreCreate, CoreOps, EU1TestData, ICTest, Ports, Rope, TerminalIO
    = BEGIN OPEN ICTest;

    Vdd: NAT = 0;
    Gnd: NAT = 1;
    PadVdd: NAT = 2;
    PadGnd: NAT = 3;
    PhA: NAT = 4;
    PhB: NAT = 5;
    nPhA: NAT = 6;
    nPhB: NAT = 7;
    KBus: NAT = 8;  -- 32 bits
    EPData: NAT = 9;  -- 32 bits
    nRejectBA: NAT = 10;
    nHold2BA: NAT = 11;
    EURes3IsPBus3AB: NAT = 12;
    EUWriteToPBus3AB: NAT = 13;
    DExecute: NAT = 14;
    DStateAddress: NAT = 15;  -- 4 bits
    EPDataEnableWrite: NAT = 16;
    KBusEnableWrite: NAT = 17;
    EUAluOp2AB: NAT = 18;  -- 4 bits, Dragon.ALUOps
    EULoadField3BA: NAT = 19;

    groups: LIST OF ICTest.Group _ EU1TestData.groups;
assignments: LIST OF ICTest.Assignments _ EU1TestData.assignments;

    public: Core.Wire;
    wordSize: NAT = 32;

    Init: PROC = {
        ct: Core.CellType _ CoreCreate.Cell[
            name: "EU1",
            public: CoreCreate.WireList[LIST[
                "Vdd", "Gnd", "PadVdd", "PadGnd", "PhA", "PhB", "nPhA", "nPhB", CoreCreate.Seq["KBus", wordSize], CoreCreate.Seq["EPData", 
                wordSize], "nRejectBA", "nHold2BA", "EURes3IsPBus3AB", "EUWriteToPBus3AB", "DExecute", 
                CoreCreate.Seq["DStateAddress", 4], "EPDataEnableWrite", "KBusEnableWrite", CoreCreate.Seq["EUAluOp2AB", 5], 
                "EULoadField3BA"]],
            onlyInternal: NIL,
            instances: NIL
            ];
        [] _ Ports.InitPort[ct.public[KBus], lc];
        [] _ Ports.InitPort[ct.public[EPData], lc];
        [] _ Ports.InitPort[ct.public[DStateAddress], c];
        [] _ Ports.InitPort[ct.public[EUAluOp2AB], c];

        Ports.InitTesterDrive[ct.public[Vdd], force];
        Ports.InitTesterDrive[ct.public[Gnd], force];
        Ports.InitTesterDrive[ct.public[PadVdd], force];
        Ports.InitTesterDrive[ct.public[PadGnd], force];
        Ports.InitTesterDrive[ct.public[PhA], force];
        Ports.InitTesterDrive[ct.public[PhB], force];
        Ports.InitTesterDrive[ct.public[nPhA], force];
        Ports.InitTesterDrive[ct.public[nPhB], force];
        Ports.InitTesterDrive[ct.public[KBus], none];
        Ports.InitTesterDrive[ct.public[EPData], none];
        Ports.InitTesterDrive[ct.public[nRejectBA], force];
        Ports.InitTesterDrive[ct.public[nHold2BA], force];
        Ports.InitTesterDrive[ct.public[EURes3IsPBus3AB], force];
        Ports.InitTesterDrive[ct.public[EUWriteToPBus3AB], force];
        Ports.InitTesterDrive[ct.public[DExecute], force];
        Ports.InitTesterDrive[ct.public[DStateAddress], force];
        Ports.InitTesterDrive[ct.public[EPDataEnableWrite], force];
        Ports.InitTesterDrive[ct.public[KBusEnableWrite], force];
        Ports.InitTesterDrive[ct.public[EUAluOp2AB], force];
        Ports.InitTesterDrive[ct.public[EULoadField3BA], force];

        Ports.InitTesterDrive[ct.public[KBus], force]; --to make TestCable easier
        Ports.InitTesterDrive[ct.public[EPData], force];
        public _ ct.public;

        ICTest.MakeStandardViewer[name: "EU1 Tester", cellType: ct, testButtons: LIST[["TestEU1", TestEU1], ["TestCable", TestCable], 
        ["LoadTest", LoadTest]], groups: groups, assignments: assignments];
        };

    TestEU1: TestProc = {
        AssembleK: PROC [a, b, c, left, right, st2A, st3A, r3A: NAT _ 0] RETURNS [LONG CARDINAL] ~ {
            RETURN[(((a*256+b)*256)+c)*256+(((left*4+right)*4+st2A)*2+st3A)*2+r3A]
            };
        PHa: PROC [] RETURNS [] ~ {
            p[nPhA].b _ FALSE;
            p[PhA].b _ TRUE;
            Eval[force];
            p[PhA].b _ FALSE;
            p[nPhA].b _ TRUE;
            Eval[sense];
            };
        PHb: PROC [] RETURNS [] ~ {
            p[nPhB].b _ FALSE;
            p[PhB].b _ TRUE;
            Eval[force];
            p[PhB].b _ FALSE;
            p[nPhB].b _ TRUE;
            Eval[sense];
            };
        p[KBus].d _ force;
        p[KBus].lc _ AssembleK[st2A: 2, st3A: 0];
        p[EPData].d _ force;
        p[EPData].lc _ 42H;
        p[nRejectBA].b _ TRUE;
        p[nHold2BA].b _ TRUE;
        p[EURes3IsPBus3AB].b _ TRUE;
        p[EUWriteToPBus3AB].b _ FALSE;
        p[EPDataEnableWrite].b _ FALSE;
        p[KBusEnableWrite].b _ FALSE;
        p[EUAluOp2AB].c _ 0;
        p[EULoadField3BA].b _ FALSE;

        PHb[];
        PHa[];
        PHb[];
        PHa[];
        PHb[];    -- 42 in r3B
        PHa[];    -- 42 in st2A
        PHb[];    -- 42 in st2B
        PHa[];    -- 42 in st3A
        p[EPData].d _ expect;
        p[EPData].lc _ 42H;
        p[EURes3IsPBus3AB].b _ FALSE;
        p[EUWriteToPBus3AB].b _ TRUE;
        p[EPDataEnableWrite].b _ TRUE;
        PHb[];    -- 42 should come out on EPData
        };

    TestCable: TestProc = {
        EachPair: PROC [wire: Core.Wire, port: Ports.Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE] 
        --Ports.EachPortPairProc-- = {
            Cycle: PROC = {
                p[KBus].d _ force;
                p[EPData].d _ force;
                Eval[force]; 
                p[KBus].d _ expect;
                p[EPData].d _ expect;
                Eval[sense];
                };
            IF port#NIL THEN port.d _ force;
            IF CoreOps.IsFullWireName[public, wire, a.name] AND a.group#0 THEN {
                IF port=NIL THEN 
                    SELECT rootPort.type FROM
                        ls => {};
                        bs => {};
                        c => {rootPort.c _ Basics.BITSHIFT[08000h, -rootPort.fieldStart-count]; Cycle[];
                            rootPort.c _ 0; Cycle[]};
                        lc => {rootPort.lc _ Basics.DoubleShift[[lc[080000000h]], -rootPort.fieldStart-count].lc; Cycle[];
                            rootPort.lc _ 0; Cycle[]};
                        ENDCASE => ERROR
                    ELSE
                        SELECT port.type FROM
                            l => {port.l _ L; Cycle[]; port.l _ H; Cycle[]};
                            b => {port.b _ TRUE; Cycle[]; port.b _ FALSE; Cycle[]};
                            ENDCASE => ERROR
                } ELSE IF port#NIL THEN SELECT port.type FROM
                    l => port.l _ L;
                    ls => {};
                    b => port.b _ FALSE;
                    bs => {};
                    c => port.c _ 0;
                    lc => port.lc _ 0;
                    ENDCASE;
            IF port#NIL AND port.type#composite THEN {count _ 0; rootPort _ port}
                ELSE count _ count+1;
            };

        probe: INT _ 1;
        count: NAT _ 0;
        a: ICTest.Assignments;
        rootPort: Ports.Port;
        TerminalIO.WriteRope["\n\nProbe Card Tester\n"];
    WHILE probe <= LAST[ProbeCardPin] DO
        FOR l: LIST OF ICTest.Assignments _ assignments, l.rest WHILE l#NIL DO
            a _ l.first;
            IF a.probeCardPin = probe THEN EXIT;
            ENDLOOP;
        IF a.probeCardPin = probe THEN {
            SELECT TRUE FROM
                Rope.Equal[s1: a.name, s2: "vdd", case: FALSE] => {
                    TerminalIO.WriteRope[IO.PutFR["Pin %g is Vdd\n", IO.int[probe]]];
                    probe _ probe+1;
                    };
                Rope.Equal[s1: a.name, s2: "gnd", case: FALSE] => {
                    TerminalIO.WriteRope[IO.PutFR["Pin %g is Gnd\n", IO.int[probe]]];
                    probe _ probe+1;
                    };
                a.group=0 => {
                    TerminalIO.WriteRope[IO.PutFR["Pin %g is unused, %g\n", IO.int[probe], IO.rope[a.name]]];
                    probe _ probe+1;
                    };
                ENDCASE => {
                    TerminalIO.WriteRope[IO.PutFR["Ready to test pin %g, %g ...", IO.int[probe], IO.rope[a.name]]];
                    SELECT TerminalIO.RequestChar[""] FROM
                        'b, 'B => {
                            probe _ probe-1;
                            TerminalIO.WriteRope["\n"];
                            };
                        'j, 'J => { --jump
                            probe _ TerminalIO.RequestInt["\nJump to pin: "];
                            IF probe < 1 THEN probe _ 1;
                            IF probe >LAST[ProbeCardPin] THEN probe _ LAST[ProbeCardPin];
                            LOOP;
                            };
                        'q, 'Q => GOTO quit;
                        'r, 'R => probe _ probe; --redo
                        ENDCASE => {
                            probe _ probe+1;
                            };
                    [] _ Ports.VisitBinding[public, p, EachPair];
                    TerminalIO.WriteRope["done\n"];
                    };
            } ELSE {
                TerminalIO.WriteRope[IO.PutFR["Pin %g not found\n", IO.int[probe]]];
                probe _ probe+1;
                };
        ENDLOOP;
        EXITS
            quit => {};
        };

    repeat: NAT _ 3;
    LoadTest: TestProc = {
        Cycle: PROC = {Eval[force]; Eval[sense]};
        EachPair: PROC [wire: Core.Wire, port: Ports.Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE] 
        --Ports.EachPortPairProc-- = {
            IF port#NIL THEN {
                port.d _ force;
                SELECT port.type FROM
                    composite => {};
                    ls => {};
                    bs => {};
                    c => port.c _ IF high THEN 0ffffh ELSE 0;
                    lc => port.lc _ IF high THEN 0ffffffffh ELSE 0;
                    l => port.l _ IF high THEN H ELSE L;
                    b => port.b _ high;
                    ENDCASE => ERROR;
                };
            };
        high: BOOL;
        FOR i: NAT IN [0..repeat) DO
            high _ TRUE;
            [] _ Ports.VisitBinding[public, p, EachPair];
            Cycle[];
            high _ FALSE;
            [] _ Ports.VisitBinding[public, p, EachPair];
            Cycle[];
            ENDLOOP;
        };

    Init[];

    END.