<> <> <> DIRECTORY DM, DMSmallCacheModel, DMMBusModel, DMPBusModel, DragOpsCrossUtils, IO, PrintTV, Rope; DMSmallCacheModelImpl: CEDAR PROGRAM IMPORTS DMPBusModel, DragOpsCrossUtils, IO, PrintTV EXPORTS DMSmallCacheModel = BEGIN OPEN DMSmallCacheModel; lineAdrs: LineName; lineAdrsValid: BOOL; Create: PUBLIC PROC [pbus, mbus: DM.Component] RETURNS [cache: DM.Component] = { <> <<>> <> cache _ NEW [DM.ComponentRec _ [ action: [Reset, PhA, EvPhA, PhB, EvPhB], history: NIL, componentType: $SmallCache, subComponents: NIL, specific: NEW [CacheSpecificRec _ [ pbus: pbus, mbus: mbus ]] ]]; }; PhA: DM.ActionProc = { cs: CacheSpecific _ NARROW[component.specific]; <> }; EvPhA: DM.ActionProc = { cs: CacheSpecific _ NARROW[component.specific]; cs.pbusOp _ DMPBusModel.Cmd[cs.pbus]; IF cs.mbusHasSC THEN { } ELSE MatchCam[cs]; }; PhB: DM.ActionProc = { cs: CacheSpecific _ NARROW[component.specific]; IF cs.pbusOp = Fetch THEN DMPBusModel.DrData[cs.pbus, ReadRam[cs]]; DMPBusModel.DrReject[cs.pbus, Reject[cs]] }; EvPhB: DM.ActionProc = { cs: CacheSpecific _ NARROW[component.specific]; IF (DMPBusModel.Cmd[cs.pbus] = Store) AND (~ cs.mbusHasSC) THEN WriteRam[cs, DMPBusModel.Data[cs.pbus]] }; Reset: DM.ActionProc = { cs: CacheSpecific _ NARROW[component.specific]; cs.mbusHasSC _ FALSE; FOR i: INT IN [1..cs.nLines] DO cs.cam[i].valid _ FALSE ENDLOOP; <> cs.cam[1].valid _ TRUE; cs.cam[1].va _ DragOpsCrossUtils.IntToWord[1]; cs.cam[1].shared _ FALSE; cs.cam[1].master _ FALSE; cs.cam[2].valid _ TRUE; cs.cam[2].va _ DragOpsCrossUtils.IntToWord[2]; cs.cam[2].shared _ FALSE; cs.cam[2].master _ FALSE; cs.cam[3].valid _ TRUE; cs.cam[3].va _ DragOpsCrossUtils.IntToWord[3]; cs.cam[3].shared _ FALSE; cs.cam[3].master _ FALSE; PrintTV.RegisterTVPrintProc[type: CODE[RamType], proc: PrintRam]; PrintTV.RegisterTVPrintProc[type: CODE[CamType], proc: PrintCam]; }; MatchCam: PROC [cs: CacheSpecific] = { lineAdrsValid _ FALSE; FOR i: INT IN [1..cs.nLines] DO IF cs.cam[i].va = DMPBusModel.Data[cs.pbus] THEN { lineAdrsValid _ TRUE; lineAdrs _ i; RETURN} ENDLOOP; <<>> }; PrintCam: PrintTV.TVPrintProc = { <<[tv: TV, data: REF ANY, stream: STREAM, depth: INT _ 4, width: INT _ 32, verbose: BOOL _ FALSE] RETURNS [useOld: BOOL _ FALSE]>> stream.PutF["cam: ... "] }; ReadRam: PROC [cs: CacheSpecific] RETURNS [data: DM.Word] = { IF lineAdrsValid THEN RETURN [cs.ram[lineAdrs]]; }; WriteRam: PROC [cs: CacheSpecific, value: DM.Word] = { IF lineAdrsValid THEN cs.ram[lineAdrs] _ value; }; PrintRam: PrintTV.TVPrintProc = { <<[tv: TV, data: REF ANY, stream: STREAM, depth: INT _ 4, width: INT _ 32, verbose: BOOL _ FALSE] RETURNS [useOld: BOOL _ FALSE]>> stream.PutF["ram: ... "] }; Reject: PROC [cs: CacheSpecific] RETURNS [BOOL] = { RETURN[ ~lineAdrsValid OR cs.mbusHasSC]; }; END.