Arithmetic Unit Data Sheet Release as /Indigo/Dragon/Documentation/AUDoc.tioga Came from /Firedrake/Cedar/AUDoc.tioga Last edited by Curry, August 29, 1985 10:26:37 am PDT DRAFT Introduction The Dragon processor is made up of three chips: IFU, EU and AU (Instruction Fetch, Execution and Arithmetic Units). The Arithmetic unit provides hardware acceleration for both floating point and fixed point operations and may or may not be present in any particular processor. It connects to the rest of the processor only through the DPBus. It transmits data to and from the EU over the DPBus data lines, listens to PBus commands, and causes variable execution delays and exception control using the DPBus Reject and Fault lines. Description Capablities Operands from the EU Statck. Results to the EU Stack or AU operand register (internal feedback of previous results). Floating point operations: Both single and double precision operands Both normal and Lisp single precision reals Add, Sub, Mult, Div, Compare, CompZero, Integer, Float The result of compare operation is a single precision INT in the range [-1..+1] Fixed point operations: Multiply (single * single -> double) Divide (double / single -> single, single) Operational Model The current state of the device is represented by 7 wds: Control: Mask, Flags, Mode and Function bytes (unmasked flags trigger AUFault) Left: Left operand Leftx: Left operand extended (least significant word) Right: Right operand Rightx: Right operand extended (least significant word) Result: Result Resultx: Result extended (least significant word) The two result words are strictly a function of the two operands and the Control register. For a process switch, 5 wds (operands and Control) need to be read/restored. Writing new state implies a possible change in the two dependent result words. The current state can be written and read in any order except: Writing result words is a nop since result words are a function on the other state. Reading result words enables Control.Flags to change. Writing new state never rejects or faults. The device is always trying to compute the result words corresponding to the current state. Any write causes the computation to begin again with the new state. Reading an operand or Control never rejects or faults. Upon reading the result: DPBus Reject will be asserted if and while the computation is incomplete. One or more of the flags may change. Unmasked flags will trigger the AUFault on the DPBus. If AUFault does not occur, then either: A result word is moved to the EU stack Both result words are moved to either the left or right operand words Two Dragon Instructions AUMV ArgOp Arithmetic Unit Move AUOP ArgOp FuncOp Arithmetic Unit (Move and) Op Both instructions take one cycle to execute. (except when the computation is incomplete and a result is being read (codes 6,7,14,15)) ArgOp (the alpha byte) Contains the 6 bit PBus Command for the instruction Specifies movement of register and both DPBus phA and phB data ArgOp Format: twoBitZeroPad: 2 Bits PBusCommand: 6 Bits TRUE: 1 Bit AU PBus Operation WriteFunc: 1 Bit Control.Function _ DPBus phA Code: 4 Bits AU Code 0000: Left _ DPBus phB 0001: Left _ DPBus phB; Leftx _ DPBus phA 0010: Right _ DPBus phB 0011: Right _ DPBus phB; Rightx _ DPBus phA 0100: Control _ DPBus phB 0101: Left _ DPBus phB; Right _ DPBus phA 0110: Left _ Result; Leftx _ Resultx 0111: Right _ Result; Rightx _ Resultx 1000: DPBus phB _ Left 1001: DPBus phB _ Leftx 1010: DPBus phB _ Right 1011: DPBus phB _ Rightx 1100: DPBus phB _ Control 1101: 1110: DPBus phB _ Result 1111: DPBus phB _ Resultx WriteFunc means that an AUOP instruction is being executed. Codes 1,3 and 5 can only be generated using AUMV (WriteFunc is not allowed to be true if DPBus phA is being used to move data). For AUOP, the FuncOp byte is written into the Function portion of the AU's Control register in phA. Therefore, if for some crazy reason ArgOp specifies writing the Control register in phB then phB's effect prevails. FuncOp is put onto DPBus during phA. From there it is written into Control.Function. FuncOp Format: IEEEReals/LispReals: 1 bit Single/Double: 1 bit Float/Integer: 1 bit Add/Sub/Mult/Div/Comp/CompZero/Float/Int: 3 bits Control Register Format: Mask byte: spare 3 Fixed Divide OverFlow Floating Inexact Result Floating UnderFlow Floating OverFlow Floating Divide by Zero Floating Invalid Operation Flag byte: spare 3 Fixed Divide OverFlow Floating Inexact Result Floating UnderFlow Floating OverFlow Floating Divide by Zero Floating Invalid Operation Mode byte: spare 4 Default Rounding Mode: 2 bits Integer Round toward Zero: 1 bit Floating Round to Zero on underflow: 1 bit Function byte: spare 2 IEEEReals/LispReals: 1 bit Single/Double: 1 bit Float/Integer: 1 bit Add/Sub/Mult/Div/Comp/CompZero/Float/Int: 3 bits Signal Naming Conventions Most signal root names have a two or three character suffix which provides timing information. The first of these characters is a number which indicates the elapsed cycles since the instruction which generated the signal entered the pipeline. The letter(s) following this number can be any of the following: (A, B, AB, BA). The first letter indicates in what phase the signal is generated. The presence of the second letter indicates that the signal is stable throughout the next phase. The absence of the second letter indicates that the signal is undefined during the next phase. Except where noted, signals generated in a particular phase are only expected to be stable at the end of that phase (in time to meet latch setup times of the receiving device). Names for the individual bits of multi-bit signals and busses are derived from the root name by appending a period and zero filled octal integers. For instance, the most significant and least significant bits of the 32 bit KBus are named KBus.00 and KBus.37 respectively whereas the most significant bit of the 5 bit (1 octal digit) wide EUAluOp2AB is EUAluOp2AB.0. Positive logic is assumed (asserted = TRUE = 1 = more positive logic voltage); negative-logic signals have an extra "N" at or very near the beginning of the signal name (e.g., DNSelectAB for DBus Negative-TRUE Select) Signal (Root) Names (pins #'s very tentative) Signal Size Pins I/O Notes MSB LSB DPRejectB 1 97 O PBus Reject DPFaultB 4 98 101 O PBus Fault DPCmnd3A 6 102 107 I PBus command from IFU DPData.20 - DPData.37 16 125 110 I/O PBus address to or data from EU DPData.00 - DPData.17 16 143 128 I/O PBus address to or data from EU VDD 1 1 GND 1 18 VDD 1 19 GND 1 36 VDD 1 37 GND 1 54 VDD 1 55 GND 1 72 VDD 1 73 GND 1 90 VDD 1 91 GND 1 108 VDD 1 109 GND 1 126 VDD 1 127 GND 1 144 Reset 1 20 I Reset control Clock 1 23 I Clock PhaseClockSel 1 24 I Use AB clocks (debug) ExplicitPhA 1 25 I Clock phase A (debug) ExplicitPhB 1 26 I Clock phase B (debug) DHoldAB 1 28 I Serial Debug Hold command DShiftAB 1 29 I Serial Debug Shift command DExecuteAB 1 30 I Serial Debug Execute command DNSelectAB 1 31 I Serial Debug Chip Select control DDataInAB 1 32 I Serial Debug Data in DDataOutAB 1 33 O Serial Debug Data out 8 GND 8 VDD xx spares Packaging The AU will be packaged in a 144 pin PGA. Bonding pad numbering: | | | | | 144 109 | | | | |1 | 108 | | |2 | | | | | | | | | | | | | | | | | | | | | | | |36 | 73 | | | | 37 72 | | | | | Package pin numbering: See /Indigo/Dragon/Documentation/PinOut144.sil Timing Set-up times and hold times with respect to clock phases: . . . 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