The Dragon processor is made up of three chips: IFU, EU and AU (Instruction Fetch, Execution and Arithmetic Units). The Arithmetic unit provides hardware acceleration for both floating point and fixed point operations and may or may not be present in any particular processor. It connects to the rest of the processor only through the DPBus. It transmits data to and from the EU over the DPBus data lines, listens to PBus commands, and causes variable execution delays and exception control using the DPBus Reject and Fault lines.

Most signal root names have a two or three character suffix which provides timing information. The first of these characters is a number which indicates the elapsed cycles since the instruction which generated the signal entered the pipeline. The letter(s) following this number can be any of the following: (A, B, AB, BA). The first letter indicates in what phase the signal is generated. The presence of the second letter indicates that the signal is stable throughout the next phase. The absence of the second letter indicates that the signal is undefined during the next phase.

Except where noted, signals generated in a particular phase are only expected to be stable at the end of that phase (in time to meet latch setup times of the receiving device).

Names for the individual bits of multi-bit signals and busses are derived from the root name by appending a period and zero filled octal integers. For instance, the most significant and least significant bits of the 32 bit KBus are named KBus.00 and KBus.37 respectively whereas the most significant bit of the 5 bit (1 octal digit) wide EUAluOp2AB is EUAluOp2AB.0.

Positive logic is assumed (asserted = TRUE = 1 = more positive logic voltage); negative-logic signals have an extra "N" at or very near the beginning of the signal name (e.g., DNSelectAB for DBus Negative-TRUE Select)