DIRECTORY Core, CoreClasses, CoreFlat, RefTab, Rope, Sisyph, SymTab; XilinxIO: CEDAR DEFINITIONS = BEGIN ROPE: TYPE = Rope.ROPE; LOR: TYPE = LIST OF ROPE; Axis: TYPE = {ax,ay}; Loc: PROC [cx: Sisyph.Context, x, y: INT] RETURNS [trash: NAT _ 0]; Set: PROC [cx: Sisyph.Context, x, y: INT, axis: Axis _ ax] RETURNS [trash: NAT _ 0]; Seq: PROC [cx: Sisyph.Context, axis: Axis, startIndex, orthogonalIndex: NAT, delta: INT _ 1] RETURNS [trash: NAT _ 0]; SaveCellType: PROC [cellType: Core.CellType, fileName: ROPE _ NIL] RETURNS [multiplyDriven: LIST OF ROPE _ NIL]; RegisterPrimitive: PROC [coreName: ROPE, proc: TranslateProc, data: REF ANY _ NIL]; MakeBindList: PROC [public: Core.Wire] RETURNS [bindlist: BindList _ NIL] ; GetParameters: PROC [symbol: Symbol, instance: CoreClasses.CellInstance]; CreateSignal: PROC [circuit: FlatCircuit, name: ROPE _ NIL] RETURNS [signal: Signal]; CreateBoundSignal: PROC [wire: Core.Wire, circuit: FlatCircuit, root: Core.CellType, flatWireToSignal: RefTab.Ref, bindings: RefTab.Ref, flatCell: CoreFlat.FlatCellTypeRec] RETURNS [signal: Signal]; AddSymbol: PROC [circuit: FlatCircuit, name, type: ROPE, bindings: PinSignals] RETURNS [symbol: Symbol]; MakeSymbol: PROC [name, type: ROPE, bind: BindList, pins: Pins, circuit: FlatCircuit, root: Core.CellType, flatCell: CoreFlat.FlatCellTypeRec, flatWireToSignal, bindings: RefTab.Ref, parameters, configs: LOR _ NIL] RETURNS [symbol: Symbol]; PinRecListToPinList: PROC [pins: PinRecList] RETURNS [refPins: Pins _ NIL]; BindList: TYPE = LIST OF RECORD[wire: Core.Wire, name: ROPE]; Primitive: TYPE = REF PrimitiveRec; PrimitiveRec: TYPE = RECORD [ translate: TranslateProc, data: REF ANY]; TranslateProc: TYPE = PROC [circuit: FlatCircuit, root, cell: Core.CellType, instance: CoreClasses.CellInstance, name: ROPE, flatCell: CoreFlat.FlatCellTypeRec, flatWireToSignal, bindings: RefTab.Ref, part2000: BOOL, data: REF ANY]; FlatCircuit: TYPE = REF FlatCircuitRec; FlatCircuitRec: TYPE = RECORD [ nameCount: INT _ 0, nameTable: SymTab.Ref _ NIL, symbols: Symbols _ NIL, signals: Signals _ NIL, partType: ROPE _ NIL]; Symbols: TYPE = LIST OF Symbol; Symbol: TYPE = REF SymbolRec; SymbolRec: TYPE = RECORD [ name: ROPE _ NIL, type: ROPE _ NIL, connections: SymbolSignalPins _ NIL, parameters: LOR _ NIL, configs: LOR _ NIL]; SymbolSignalPins: TYPE = LIST OF SymbolSignalPin; SymbolSignalPin: TYPE = REF SymbolSignalPinRec; SymbolSignalPinRec: TYPE = RECORD [ symbol: Symbol _ NIL, signal: Signal _ NIL, pin: Pin _ NIL, parameters: LOR _ NIL]; Signals: TYPE = LIST OF Signal; Signal: TYPE = REF SignalRec; SignalRec: TYPE = RECORD [ name: ROPE _ NIL, connections: SymbolSignalPins _ NIL, pin: ROPE _ NIL, -- NIL => not forced unbonded: BOOL _ FALSE, parameters: LOR _ NIL]; PinSignals: TYPE = LIST OF PinSignalRec; PinSignalRec: TYPE = RECORD [ pin: Pin _ NIL, signal: Signal _ NIL]; Pins: TYPE = LIST OF Pin; PinRecList : TYPE = LIST OF PinRec; Pin: TYPE = REF PinRec; PinRec: TYPE = RECORD [ coreName: Rope.ROPE, xilinxName: Rope.ROPE, direction: InOrOut, physicalPin: BOOL _ FALSE, tristate: BOOL _ FALSE, invert: BOOL _ FALSE]; InOrOut: TYPE = {In, Out}; END. าXilinxIO.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Barth, February 14, 1990 5:21:06 pm PST Placement IO fileName=NIL => fileName _ Rope.Cat[CoreOps.GetCellTypeName[cellType], ".xnf"] Types Primitive Data Base Flattened Circuit some connections' pin.physicalPin = TRUE causes an EXT record to be emitted using unbonded, pin, and parameters all connections' pin.physicalPin = FALSE and parameters#NIL causes a SIG record to be emitted สX˜codešœ ™ Kšœ ฯmœ1™