Simple
SimpleData: TYPE = REF SimpleDataRec;
SimpleDataRec:
TYPE =
RECORD [
xilinxType: ROPE,
pins: Pins];
RegisterSimplePrimitive:
PROC [coreName:
ROPE, xilinxType:
ROPE, pins: PinRecList, aliases:
LOR ←
NIL] = {
simpleData: SimpleData ←
NEW[SimpleDataRec ← [
xilinxType: xilinxType,
pins: PinRecListToPinList[pins]]];
RegisterPrimitive[coreName, FlattenSimplePrimitive, simpleData];
FOR al:
LOR ← aliases, al.rest
UNTIL al=
NIL
DO
RegisterPrimitive[al.first, FlattenSimplePrimitive, simpleData];
ENDLOOP;
};
FlattenSimplePrimitive: TranslateProc = {
simpleData: SimpleData ← NARROW[data];
symbol: Symbol ← MakeSymbol[CoreFlat.CellTypePathRope[root, flatCell], simpleData.xilinxType, MakeBindList[cell.public], simpleData.pins, circuit, root, flatCell, flatWireToSignal, bindings];
GetParameters[symbol, instance];
};
CLB
CLBData: TYPE = REF CLBDataRec;
CLBDataRec:
TYPE =
RECORD [
config: ROPE,
equate: ROPE];
clbGatePins: Pins ← PinRecListToPinList[
LIST[
["A", "A", In],
["B", "B", In],
["C", "C", In],
["D", "D", In],
["X", "X", Out]]];
RegisterCLBPrimitive:
PROC [coreName:
ROPE, config:
ROPE, equate:
ROPE] = {
clbData: CLBData ←
NEW[CLBDataRec ← [
config: config,
equate: equate]];
RegisterPrimitive[coreName, FlattenCLBGate, clbData];
};
FlattenCLBGate: TranslateProc = {
clbData: CLBData ← NARROW[data];
configs: LOR ← LIST[Rope.Cat["EQUATE F=", clbData.equate]];
symbol: Symbol;
configs ← CONS[Rope.Cat["CONFIG X:F F:", clbData.config], configs];
configs ← CONS[Rope.Cat["BASE ", IF part2000 THEN "F" ELSE "FG"], configs];
symbol ← MakeSymbol[CoreFlat.CellTypePathRope[root, flatCell], "CLB", MakeBindList[cell.public], clbGatePins, circuit, root, flatCell, flatWireToSignal, bindings, NIL, configs];
GetParameters[symbol, instance];
};
clbPins: Pins ← PinRecListToPinList[
LIST[
["A", "A", In],
["B", "B", In],
["C", "C", In],
["D", "D", In],
["E", "E", In],
["DI", "DI", In],
["CE", "CE", In],
["K", "K", In],
["R", "R", In],
["X", "X", Out],
["Y", "Y", Out]]];
FlattenCLBPrimitive: TranslateProc = {
symbol: Symbol;
equateF: ROPE ← NARROW[CoreProperties.GetCellInstanceProp[instance, $EQUATEF]];
equateG: ROPE ← NARROW[CoreProperties.GetCellInstanceProp[instance, $EQUATEG]];
configs: LOR ← NIL;
IF equateF#NIL THEN configs ← CONS[Rope.Cat["EQUATE F=", equateF], configs];
IF equateG#NIL THEN configs ← CONS[Rope.Cat["EQUATE G=", equateG], configs];
configs ← CONS[Rope.Cat["CONFIG ", NARROW[CoreProperties.GetCellInstanceProp[instance, $CONFIG]]], configs];
configs ← CONS[Rope.Cat["BASE ", NARROW[CoreProperties.GetCellInstanceProp[instance, $BASE]]], configs];
symbol ← MakeSymbol[CoreFlat.CellTypePathRope[root, flatCell], "CLB", MakeBindList[cell.public], clbPins, circuit, root, flatCell, flatWireToSignal, bindings, NIL, configs];
GetParameters[symbol, instance];
};
Flop
flopPins: Pins ← PinRecListToPinList[
LIST[
["D", "D", In],
["CK", "C", In],
["Q", "Q", Out]]];
flopEnPins: Pins ← PinRecListToPinList[
LIST[
["D", "D", In],
["CK", "C", In],
["Q", "Q", Out],
["en", "CE", In]]];
flopReg1Pins: Pins ← PinRecListToPinList[
LIST[
["Input", "D", In],
["CK", "C", In],
["Output", "Q", Out],
["en", "CE", In]]];
invPins: Pins ← PinRecListToPinList[
LIST[
["I", "I", In],
["X", "O", Out]]];
FlattenFlopPrimitive: TranslateProc = {
symbol: Symbol;
flatName: ROPE ← CoreFlat.CellTypePathRope[root, flatCell];
lora: LIST OF REF ANY ← NARROW[data];
nqName: ROPE ← CoreOps.FixStupidRef[lora.first];
pins: Pins ← NARROW[lora.rest.first];
d: Core.Wire ← CoreOps.FindWire[cell.public, pins.first.coreName];
c: Core.Wire ← CoreOps.FindWire[cell.public, pins.rest.first.coreName];
q: Core.Wire ← CoreOps.FindWire[cell.public, pins.rest.rest.first.coreName];
en: Core.Wire ← IF pins.rest.rest.rest=NIL THEN NIL ELSE CoreOps.FindWire[cell.public, pins.rest.rest.rest.first.coreName];
nq: Core.Wire ← CoreOps.FindWire[cell.public, nqName];
bindList: BindList ← LIST[[d, pins.first.coreName], [c, pins.rest.first.coreName], [q, pins.rest.rest.first.coreName]];
IF en#NIL THEN bindList ← CONS[[en, pins.rest.rest.rest.first.coreName], bindList];
symbol ← MakeSymbol[flatName, "DFF", bindList, pins, circuit, root, flatCell, flatWireToSignal, bindings];
[] ← MakeSymbol[Rope.Cat[flatName, "ManufacturedInverter"], "INV", LIST[[q, "I"], [nq, "X"]], invPins, circuit, root, flatCell, flatWireToSignal, bindings];
GetParameters[symbol, instance];
};
SymDriver
symPins: Pins ← PinRecListToPinList[
LIST[
["I", "I", In],
["X", "O", Out]]];
FlattenSymDriverPrimitive: TranslateProc = {
flatName: ROPE ← CoreFlat.CellTypePathRope[root, flatCell];
i: Core.Wire ← CoreOps.FindWire[cell.public, "I"];
x: Core.Wire ← CoreOps.FindWire[cell.public, "X"];
nx: Core.Wire ← CoreOps.FindWire[cell.public, "nX"];
[] ← MakeSymbol[Rope.Cat[flatName, "ManufacturedBuffer"], "BUF", LIST[[i, "I"], [x, "X"]], symPins, circuit, root, flatCell, flatWireToSignal, bindings];
[] ← MakeSymbol[Rope.Cat[flatName, "ManufacturedInverter"], "INV", LIST[[i, "I"], [nx, "X"]], symPins, circuit, root, flatCell, flatWireToSignal, bindings];
};
Tristate Driver
tPin: Pin ← NEW[PinRec ← ["?", "T", In]];
iPin: Pin ← NEW[PinRec ← ["I", "I", In]];
oPin: Pin ←
NEW[PinRec ← ["X", "O", Out,,
TRUE]];
FlattenTristateDriver: TranslateProc = {
symbol: Symbol;
flatName: ROPE ← CoreFlat.CellTypePathRope[root, flatCell];
en: Signal ← CreateBoundSignal[CoreOps.FindWire[cell.public, "EN"], circuit, root, flatWireToSignal, bindings, flatCell];
i: Signal ← CreateBoundSignal[CoreOps.FindWire[cell.public, "I"], circuit, root, flatWireToSignal, bindings, flatCell];
x: Signal ← CreateBoundSignal[CoreOps.FindWire[cell.public, "X"], circuit, root, flatWireToSignal, bindings, flatCell];
nenb: Signal ← CreateSignal[circuit];
[] ← AddSymbol[circuit, Rope.Cat[flatName, "ManufacturedEnableInverter"], "INV", LIST[[iPin, en], [oPin, nenb]]];
symbol ← AddSymbol[circuit, Rope.Cat[flatName, "ManufacturedTristate"], "TBUF", LIST[[tPin, nenb], [iPin, i], [oPin, x]]];
GetParameters[symbol, instance];
};
FlattenTristateDriverInv: TranslateProc = {
symbol: Symbol;
flatName: ROPE ← CoreFlat.CellTypePathRope[root, flatCell];
en: Signal ← CreateBoundSignal[CoreOps.FindWire[cell.public, "EN"], circuit, root, flatWireToSignal, bindings, flatCell];
i: Signal ← CreateBoundSignal[CoreOps.FindWire[cell.public, "I"], circuit, root, flatWireToSignal, bindings, flatCell];
x: Signal ← CreateBoundSignal[CoreOps.FindWire[cell.public, "X"], circuit, root, flatWireToSignal, bindings, flatCell];
nenb: Signal ← CreateSignal[circuit];
nd: Signal ← CreateSignal[circuit];
[] ← AddSymbol[circuit, Rope.Cat[flatName, "ManufacturedEnableInverter"], "INV", LIST[[iPin, en], [oPin, nenb]]];
[] ← AddSymbol[circuit, Rope.Cat[flatName, "ManufacturedDataInverter"], "INV", LIST[[iPin, i], [oPin, nd]]];
symbol ← AddSymbol[circuit, Rope.Cat[flatName, "ManufacturedTristate"], "TBUF", LIST[[tPin, nenb], [iPin, nd], [oPin, x]]];
GetParameters[symbol, instance];
};
Registration
Really should load the primitive definitions by scanning a cell in Xilinx.dale
I/O Symbols
RegisterSimplePrimitive["IBuf", "IBUF",
LIST[
["I", "I", In, TRUE],
["X", "O", Out]]];
RegisterSimplePrimitive["OBuf", "OBUF",
LIST[
["I", "I", In],
["X", "O", Out, TRUE]]];
RegisterSimplePrimitive["OBufZ", "OBUFZ",
LIST[
["I", "I", In],
["EN", "T", In,,,TRUE],
["X", "O", Out, TRUE, TRUE]]];
RegisterSimplePrimitive["OutFF", "OUTFF",
LIST[
["D", "D", In],
["CK", "C", In],
["Q", "Q", Out, TRUE]]];
RegisterSimplePrimitive["OutFFZ", "OUTFFZ",
LIST[
["D", "D", In],
["EN", "T", In,,,TRUE],
["CK", "C", In],
["X", "O", Out, TRUE, TRUE]]];
RegisterSimplePrimitive["InFF", "INFF",
LIST[
["D", "D", In, TRUE],
["CK", "C", In],
["Q", "Q", Out]]];
RegisterSimplePrimitive["InFFBuf", "INFF",
LIST[
["D", "D", In, TRUE],
["CK", "C", In],
["O", "O", Out],
["Q", "Q", Out]]];
RegisterSimplePrimitive["InLatch", "INLAT",
LIST[
["D", "D", In, TRUE],
["E", "L", In],
["X", "O", In],
["Q", "Q", Out]]];
Inverters, Buffers
RegisterSimplePrimitive["inv", "INV",
LIST[
["I", "I", In],
["X", "O", Out]], LIST["invP", "invB", "invPB", "invBuffer", "invDriver"]];
RegisterSimplePrimitive["driver", "BUF",
LIST[
["I", "I", In],
["X", "O", Out]]];
RegisterPrimitive["symDriver", FlattenSymDriverPrimitive, NIL];
RegisterPrimitive["3BufferI", FlattenTristateDriverInv, NIL];
RegisterPrimitive["3BufferNI", FlattenTristateDriver, NIL];
RegisterSimplePrimitive["3BufferNI", "TBUF", LIST[
["I", "I", In],
["EN", "T", In,,,TRUE],
["X", "O", Out, FALSE, TRUE]]];
RegisterSimplePrimitive["AClk", "ACLK",
LIST[
["I", "I", In],
["X", "O", Out]]];
RegisterSimplePrimitive["GClk", "GCLK",
LIST[
["I", "I", In],
["X", "O", Out]]];
Gates: 2, 3, and 4 input
RegisterSimplePrimitive["and2", "AND",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["X", "O", Out]]];
RegisterSimplePrimitive["and3", "AND",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["I-C", "3", In],
["X", "O", Out]]];
RegisterSimplePrimitive["and4", "AND",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["I-C", "3", In],
["I-D", "4", In],
["X", "O", Out]]];
RegisterSimplePrimitive["or2", "OR",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["X", "O", Out]]];
RegisterSimplePrimitive["or3", "OR",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["I-C", "3", In],
["X", "O", Out]]];
RegisterSimplePrimitive["or4", "OR",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["I-C", "3", In],
["I-D", "4", In],
["X", "O", Out]]];
RegisterSimplePrimitive["nand2", "NAND",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["X", "O", Out]]];
RegisterSimplePrimitive["nand3", "NAND",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["I-C", "3", In],
["X", "O", Out]]];
RegisterSimplePrimitive["nand4", "NAND",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["I-C", "3", In],
["I-D", "4", In],
["X", "O", Out]]];
RegisterSimplePrimitive["nor2", "NOR",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["X", "O", Out]]];
RegisterSimplePrimitive["nor3", "NOR",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["I-C", "3", In],
["X", "O", Out]]];
RegisterSimplePrimitive["nor4", "NOR",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["I-C", "3", In],
["I-D", "4", In],
["X", "O", Out]]];
RegisterSimplePrimitive["xor2", "XOR",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["X", "O", Out]]];
RegisterSimplePrimitive["xnor2", "XNOR",
LIST[
["I-A", "1", In],
["I-B", "2", In],
["X", "O", Out]]];
Gates, compound
RegisterCLBPrimitive["a22o2iP", "A:B:C:D", "~((A*B)+(C*D))"];
RegisterCLBPrimitive["a22o2i", "A:B:C:D", "~((A*B)+(C*D))"];
RegisterCLBPrimitive["o22a2iP", "A:B:C:D", "~((A+B)*(C+D))"];
RegisterCLBPrimitive["o22a2i", "A:B:C:D", "~((A+B)*(C+D))"];
RegisterCLBPrimitive["a21o2i", "A:B:C", "~((A*B)+C)"];
RegisterCLBPrimitive["o21a2i", "A:B:C", "~((A+B)*C)"];
Flops
RegisterSimplePrimitive["DFF", "DFF",
LIST[
["D", "D", In],
["ap", "SD", In],
["ar", "RD", In],
["CK", "C", In],
["Q", "Q", Out]]];
RegisterSimplePrimitive["ffAR", "DFF",
LIST[
["D", "D", In],
["ar", "RD", In],
["CK", "C", In],
["Q", "Q", Out]]];
RegisterPrimitive["ff", FlattenFlopPrimitive, LIST["NQ", flopPins]];
RegisterPrimitive["ffEn", FlattenFlopPrimitive, LIST["NQ", flopEnPins]];
RegisterPrimitive["reg1", FlattenFlopPrimitive, LIST["nOutput", flopReg1Pins]];
Misc.
RegisterSimplePrimitive["pullUp", "PULLUP",
LIST[
["out", "O", Out, FALSE, FALSE]]];
RegisterSimplePrimitive["Osc", "OSC",
LIST[
["X", "O", Out]]];
RegisterPrimitive["CLB", FlattenCLBPrimitive];